Syntax error near "context".

[mahdi259]

Describe the bug
The updated testbench contains context keyword that is not supported in older software like ISE.

To Reproduce
I used neorv32_tb.vhd file as benchmark.

Expected behavior
Normal simulation.

Screenshots

[mahdi259]

Oh. I think this testbench file is only usable by VUnit, right?

[stnolting]

The testbench files in sim require VHDL-2008 (or newer) as standard. Please use the functional-equivalent "simple" testbench in sim/simple for toolchain that do not support this standard.

Btw, we really should add a note regarding this to the README 😅

[stnolting]

Oh. I think this testbench file is only usable by VUnit, right?

Well, yes, and VUnit requires VHDL-2008 (as far as I can see).

[mahdi259]

Thanks for your reply.

[stnolting]

You're welcome! :)

[umarcor]

VUnit uses VHDL 2008 by default, but it does have a VHDL 1993 mode. The problem is that simulators from AMD/Xilinx traditionally do not support enough of VHDL 2008 to use the default, and neither support enough of VHDL 1993 to use the compatility mode. So, in order to use those tools, a non-standard variation of a 30y old version of the language needs to be used.

I would argue that it is less of a headache to use some simulator which does support VHDL 2008, such as GHDL or NVC. For synthesis, ghdl synth allows converting VHDL 2008 sources to some flavour that AMD/Xilinx can understand.

[stnolting]

For synthesis, ghdl synth allows converting VHDL 2008 sources to some flavour that AMD/Xilinx can understand.

Very good point!