[docs/datasheet] minor edits

stnolting · Dec 14, 2021 · fcfec71 · fcfec71
1 parent a452662
commit fcfec71
Showing 1 changed file with 4 additions and 3 deletions.
diff --git a/docs/datasheet/overview.adoc b/docs/datasheet/overview.adoc
@@ -278,6 +278,8 @@ This chapter shows _exemplary_ implementation results of the NEORV32 CPU and NEO
 |=======================
 | Hardware version: | `1.5.7.10`
 | Top entity:       | `rtl/core/neorv32_cpu.vhd`
+| FPGA:             | Intel Cyclone IV E `EP4CE22F17C6`
+| Toolchain:        | Quartus Prime 20.1.0
 |=======================
 
 [cols="<5,>1,>1,>1,>1,>1"]
@@ -295,9 +297,6 @@ This chapter shows _exemplary_ implementation results of the NEORV32 CPU and NEO
 | `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 |     1024 |    7 | 116 MHz
 |=======================
 
-[NOTE]
-No HPM counters and no PMP regions were implemented for generating these results.
-
 [TIP]
 The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
 counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
@@ -313,6 +312,8 @@ https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configur
 |=======================
 | Hardware version: | `1.5.7.15`
 | Top entity:       | `rtl/core/neorv32_top.vhd`
+| FPGA:             | Intel Cyclone IV E `EP4CE22F17C6`
+| Toolchain:        | Quartus Prime 20.1.0
 |=======================
 
 .Hardware utilization by the processor modules (mandatory core modules in **bold**)