🚀 preparing release v1.8.6

stnolting · Jun 27, 2023 · e736259 · e736259
1 parent d021de9
commit e736259
Show file tree

Hide file tree

Showing 4 changed files with 8 additions and 6 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -33,6 +33,7 @@ mimpid = 0x01080200 => Version 01.08.02.00 => v1.8.2
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 27.06.2023 | [**:rocket:1.8.6**](https://github.com/stnolting/neorv32/releases/tag/v1.8.6) | **New release** |
 | 24.06.2023 | 1.8.5.9 | :test_tube: VHDL code: use entity instantiation instead of component instantiation; [#637](https://github.com/stnolting/neorv32/pull/637) |
 | 24.06.2023 | 1.8.5.8 | optimize CPU control logic; closed further invalid instruction word detection holes; [#636](https://github.com/stnolting/neorv32/pull/636) |
 | 23.06.2023 | 1.8.5.7 | :warning: remove **buskeeper's status register**; [#635](https://github.com/stnolting/neorv32/pull/635) |

diff --git a/docs/attrs.adoc b/docs/attrs.adoc
@@ -1,7 +1,7 @@
 :author: by stnolting
 :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.8.5
+:revnumber: v1.8.6
 :doctype: book
 :sectnums:
 :stem:

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -60,7 +60,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080509"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080600"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!
 
@@ -323,8 +323,9 @@ package neorv32_package is
   type mem32_t is array (natural range <>) of std_ulogic_vector(31 downto 0); -- memory with 32-bit entries
   type mem8_t  is array (natural range <>) of std_ulogic_vector(07 downto 0); -- memory with 8-bit entries
 
-  -- Internal Bus Interface: Request --------------------------------------------------------
+  -- Internal Bus Interface -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
+  -- bus request --
   type bus_req_t is record
     addr : std_ulogic_vector(31 downto 0); -- access address
     data : std_ulogic_vector(31 downto 0); -- write data
@@ -335,8 +336,7 @@ package neorv32_package is
     priv : std_ulogic; -- set if privileged (machine-mode) access
   end record;
 
-  -- Internal Bus Interface: Response -------------------------------------------------------
-  -- -------------------------------------------------------------------------------------------
+  -- bus response --
   type bus_rsp_t is record
     data : std_ulogic_vector(31 downto 0); -- read data
     ack  : std_ulogic; -- access acknowledge (single-shot)
@@ -350,6 +350,7 @@ package neorv32_package is
     err  => '0'
   );
 
+
 -- ****************************************************************************************************************************
 -- RISC-V ISA Definitions
 -- ****************************************************************************************************************************

diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd
@@ -4,7 +4,7 @@
   <vendor>stnolting</vendor>
   <name>neorv32</name>
   <series>RISC-V</series>
-  <version>1.8.5</version>
+  <version>1.8.6</version>
   <description>The NEORV32 RISC-V Processor</description>
 
   <!-- CPU core -->