[rtl] fix HPM null range assertions (#803)

stnolting · Feb 10, 2024 · c8e05cb · c8e05cb
2 parents a82a450 + 1a8b9b7
commit c8e05cb
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Showing 4 changed files with 18 additions and 14 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Link |
 |:----:|:-------:|:--------|:----:|
+| 10.02.2024 | 1.9.4.9 | fixing HPM configuration's null range assertions | [#803](https://github.com/stnolting/neorv32/pull/803) |
 | 10.02.2024 | 1.9.4.8 | :bug: fix missing fence pass-through in caches | [#802](https://github.com/stnolting/neorv32/pull/802) |
 | 09.02.2024 | 1.9.4.7 | :warning: integrate fence signal into CPU bus, remove top entity's fence signals | (#800)[https://github.com/stnolting/neorv32/pull/800] |
 | 09.02.2024 | 1.9.4.6 | :sparkles: add configurable XIP cache | [#799](https://github.com/stnolting/neorv32/pull/799) |

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -302,7 +302,7 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
   signal csr : csr_t;
 
   -- hpm event configuration CSRs --
-  type hpmevent_cfg_t is array (3 to (hpm_num_c+3)-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
+  type hpmevent_cfg_t is array (3 to 15) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
   type hpmevent_rd_t  is array (3 to 15) of std_ulogic_vector(XLEN-1 downto 0);
   signal hpmevent_cfg : hpmevent_cfg_t;
   signal hpmevent_rd  : hpmevent_rd_t;
@@ -2283,7 +2283,7 @@ begin
       cnt_hi_rd(2) <= cnt.hi(2); -- instreth
     end if;
     -- hpm counters --
-    if (CPU_EXTENSION_RISCV_Zihpm = true) then
+    if (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_num_c > 0) then
       for i in 3 to (hpm_num_c+3)-1 loop
         if (hpm_cnt_lo_width_c > 0) then -- constrain low word size
           cnt_lo_rd(i)(hpm_cnt_lo_width_c-1 downto 0) <= cnt.lo(i)(hpm_cnt_lo_width_c-1 downto 0);
@@ -2299,7 +2299,7 @@ begin
   -- Hardware Performance Monitors (HPM) - Counter Event Configuration CSRs -----------------
   -- -------------------------------------------------------------------------------------------
   hpmevent_gen_enable:
-  if CPU_EXTENSION_RISCV_Zihpm generate
+  if CPU_EXTENSION_RISCV_Zihpm and (hpm_num_c > 0) generate
 
     -- write enable decoder --
     hpmevent_write: process(csr)
@@ -2340,9 +2340,8 @@ begin
 
 
   -- no HPMs implemented --
-  hpm_gen_disable:
-  if not CPU_EXTENSION_RISCV_Zihpm generate
-    hpmevent_we  <= (others => '0');
+  hpmevent_gen_disable:
+  if (not CPU_EXTENSION_RISCV_Zihpm) or (hpm_num_c = 0) generate
     hpmevent_cfg <= (others => (others => '0'));
     hpmevent_rd  <= (others => (others => '0'));
   end generate;
@@ -2357,12 +2356,16 @@ begin
     elsif rising_edge(clk_i) then
       cnt.inc <= (others => '0'); -- default
       -- base counters --
-      cnt.inc(0) <= cnt_event(hpmcnt_event_cy_c) and (not csr.mcountinhibit(0)) and (not debug_ctrl.running);
-      cnt.inc(2) <= cnt_event(hpmcnt_event_ir_c) and (not csr.mcountinhibit(2)) and (not debug_ctrl.running);
-      -- HPM counters --
-      for i in 3 to (hpm_num_c+3)-1 loop
-        cnt.inc(i) <= or_reduce_f(cnt_event and hpmevent_cfg(i)) and (not csr.mcountinhibit(i)) and (not debug_ctrl.running);
-      end loop;
+      if (CPU_EXTENSION_RISCV_Zicntr = true) then
+        cnt.inc(0) <= cnt_event(hpmcnt_event_cy_c) and (not csr.mcountinhibit(0)) and (not debug_ctrl.running);
+        cnt.inc(2) <= cnt_event(hpmcnt_event_ir_c) and (not csr.mcountinhibit(2)) and (not debug_ctrl.running);
+      end if;
+      -- hpm counters --
+      if (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_num_c > 0) then
+        for i in 3 to (hpm_num_c+3)-1 loop
+          cnt.inc(i) <= or_reduce_f(cnt_event and hpmevent_cfg(i)) and (not csr.mcountinhibit(i)) and (not debug_ctrl.running);
+        end loop;
+      end if;
     end if;
   end process counter_event;
 

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -56,7 +56,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090408"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090409"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -165,7 +165,7 @@ entity neorv32_top is
     jtag_trst_i    : in  std_ulogic := 'H'; -- low-active TAP reset (optional)
     jtag_tck_i     : in  std_ulogic := 'L'; -- serial clock
     jtag_tdi_i     : in  std_ulogic := 'L'; -- serial data input
-    jtag_tdo_o     : out std_ulogic;        -- serial data output
+    jtag_tdo_o     : out std_ulogic; -- serial data output
     jtag_tms_i     : in  std_ulogic := 'L'; -- mode select
 
     -- Wishbone bus interface (available if MEM_EXT_EN = true) --