[docs] add DMA done flag

docs/datasheet/soc_dma.adoc

@@ -54,6 +54,10 @@ Software can read the `SRC_BASE` or `DST_BASE` register to retrieve the address
 Alternatively, software can read back the `NUM` bits of the control register to determine the index of the element
 that caused the error. The error bits are automatically cleared when starting a new transfer.
 
+When the `DMA_CTRL_DONE` flag is set the DMA has actually executed a transfer. However, the `DMA_CTRL_ERROR_*` flags
+should also be checked to verify that the executed transfer completed without errors. The `DMA_CTRL_DONE` flag is
+automatically cleared when writing the `CTRL` register.
+
 [WARNING]
 Transactions performed by the DMA use _machine mode_ permissions (having full access rights) and will
 also **bypass** any physical memory protection rules (<<_pmp_isa_extension>>).
@@ -122,13 +126,14 @@ explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
 [options="header",grid="all"]
 |=======================
 | Address | Name [C] | Bit(s), Name [C] | R/W | Function
-.8+<| `0xffffed00` .8+<| `CTRL` <|`0`     `DMA_CTRL_EN`                                     ^| r/w <| DMA module enable
+.9+<| `0xffffed00` .9+<| `CTRL` <|`0`     `DMA_CTRL_EN`                                     ^| r/w <| DMA module enable
                                 <|`1`     `DMA_CTRL_AUTO`                                   ^| r/w <| Enable automatic mode (FIRQ-triggered)
                                 <|`7:2`   _reserved_                                        ^| r/- <| reserved, read as zero
                                 <|`8`     `DMA_CTRL_ERROR_RD`                               ^| r/- <| Error during read access, clears when starting a new transfer
                                 <|`9`     `DMA_CTRL_ERROR_WR`                               ^| r/- <| Error during write access, clears when starting a new transfer
                                 <|`10`    `DMA_CTRL_BUSY`                                   ^| r/- <| DMA transfer in progress
-                                <|`15:11` _reserved_                                        ^| r/- <| reserved, read as zero
+                                <|`11`    `DMA_CTRL_DONE`                                   ^| r/c <| Set if a transfer was executed; auto-clears on write-access
+                                <|`15:12` _reserved_                                        ^| r/- <| reserved, read as zero
                                 <|`31:16` `DMA_CTRL_FIRQ_MASK_MSB : DMA_CTRL_FIRQ_MASK_LSB` ^| r/w <| FIRQ trigger mask (same bits as in <<_mip>>)
 | `0xffffed04` | `SRC_BASE` |`31:0` | r/w | Source base address (shows the last-accessed source address when read)
 | `0xffffed08` | `DST_BASE` |`31:0` | r/w | Destination base address (shows the last-accessed destination address when read)