[rtl] FIFO remove redundant output register

for sync FIFO with just a single entry
stnolting · Jun 23, 2024 · 8ab8b97 · 8ab8b97
1 parent c0b8020
commit 8ab8b97
Showing 1 changed file with 1 addition and 6 deletions.
diff --git a/rtl/core/neorv32_fifo.vhd b/rtl/core/neorv32_fifo.vhd
@@ -222,12 +222,7 @@ begin
     -- just 1 FIFO entry --
     fifo_read_sync_small:
     if (fifo_depth_c = 1) generate
-      sync_read_small: process(clk_i)
-      begin
-        if rising_edge(clk_i) then
-          rdata_o <= fifo_reg;
-        end if;
-      end process sync_read_small;
+      rdata_o <= fifo_reg;
     end generate;
 
     -- more than 1 FIFO entry --