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[LiteX wrapper] typo fix
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stnolting committed Apr 15, 2024
1 parent 891aed6 commit 8012758
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2 changes: 1 addition & 1 deletion rtl/system_integration/neorv32_litex_core_complex.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
);

-- misc --
signal wb_cyc : std_ulogic:
signal wb_cyc : std_ulogic;

begin

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