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[top] add SLINK routing information ports
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src = AXI-S "TID"
dst = AXI-S "TDEST"
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@stnolting
stnolting committed May 21, 2024
1 parent 6f9abc9 commit 7acd7d0
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Showing 3 changed files with 40 additions and 29 deletions.
30 changes: 16 additions & 14 deletions rtl/core/neorv32_package.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ package neorv32_package is

-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090901"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090902"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

Expand Down Expand Up @@ -119,15 +119,15 @@ package neorv32_package is
-- Internal Memory Types ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
type mem32_t is array (natural range <>) of std_ulogic_vector(31 downto 0); -- memory with 32-bit entries
type mem8_t is array (natural range <>) of std_ulogic_vector(07 downto 0); -- memory with 8-bit entries
type mem8_t is array (natural range <>) of std_ulogic_vector(7 downto 0); -- memory with 8-bit entries

-- Internal Bus Interface -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- bus request --
type bus_req_t is record
addr : std_ulogic_vector(31 downto 0); -- access address
data : std_ulogic_vector(31 downto 0); -- write data
ben : std_ulogic_vector(03 downto 0); -- byte enable
ben : std_ulogic_vector(3 downto 0); -- byte enable
stb : std_ulogic; -- request strobe (single-shot)
rw : std_ulogic; -- 0=read, 1=write
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
Expand Down Expand Up @@ -167,8 +167,8 @@ package neorv32_package is
-- -------------------------------------------------------------------------------------------
-- request --
type dmi_req_t is record
addr : std_ulogic_vector(06 downto 0);
op : std_ulogic_vector(01 downto 0);
addr : std_ulogic_vector(6 downto 0);
op : std_ulogic_vector(1 downto 0);
data : std_ulogic_vector(31 downto 0);
end record;

Expand Down Expand Up @@ -483,27 +483,27 @@ package neorv32_package is
type ctrl_bus_t is record
-- register file --
rf_wb_en : std_ulogic; -- write back enable
rf_rs1 : std_ulogic_vector(04 downto 0); -- source register 1 address
rf_rs2 : std_ulogic_vector(04 downto 0); -- source register 2 address
rf_rd : std_ulogic_vector(04 downto 0); -- destination register address
rf_rs1 : std_ulogic_vector(4 downto 0); -- source register 1 address
rf_rs2 : std_ulogic_vector(4 downto 0); -- source register 2 address
rf_rd : std_ulogic_vector(4 downto 0); -- destination register address
rf_zero_we : std_ulogic; -- allow/force write access to x0
-- alu --
alu_op : std_ulogic_vector(02 downto 0); -- operation select
alu_op : std_ulogic_vector(2 downto 0); -- operation select
alu_sub : std_ulogic; -- addition/subtraction control
alu_opa_mux : std_ulogic; -- operand A select (0=rs1, 1=PC)
alu_opb_mux : std_ulogic; -- operand B select (0=rs2, 1=IMM)
alu_unsigned : std_ulogic; -- is unsigned ALU operation
alu_cp_trig : std_ulogic_vector(05 downto 0); -- co-processor trigger (one-hot)
alu_cp_trig : std_ulogic_vector(5 downto 0); -- co-processor trigger (one-hot)
-- load/store unit --
lsu_req : std_ulogic; -- trigger memory access request
lsu_rw : std_ulogic; -- 0: read access, 1: write access
lsu_mo_we : std_ulogic; -- memory address and data output register write enable
lsu_fence : std_ulogic; -- fence(.i) operation
lsu_priv : std_ulogic; -- effective privilege mode for load/store
-- instruction word --
ir_funct3 : std_ulogic_vector(02 downto 0); -- funct3 bit field
ir_funct3 : std_ulogic_vector(2 downto 0); -- funct3 bit field
ir_funct12 : std_ulogic_vector(11 downto 0); -- funct12 bit field
ir_opcode : std_ulogic_vector(06 downto 0); -- opcode bit field
ir_opcode : std_ulogic_vector(6 downto 0); -- opcode bit field
-- cpu status --
cpu_priv : std_ulogic; -- effective privilege mode
cpu_sleep : std_ulogic; -- set when CPU is in sleep mode
Expand Down Expand Up @@ -818,18 +818,20 @@ package neorv32_package is
xbus_adr_o : out std_ulogic_vector(31 downto 0);
xbus_dat_o : out std_ulogic_vector(31 downto 0);
xbus_we_o : out std_ulogic;
xbus_sel_o : out std_ulogic_vector(03 downto 0);
xbus_sel_o : out std_ulogic_vector(3 downto 0);
xbus_stb_o : out std_ulogic;
xbus_cyc_o : out std_ulogic;
xbus_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'L');
xbus_ack_i : in std_ulogic := 'L';
xbus_err_i : in std_ulogic := 'L';
-- Stream Link Interface (available if IO_SLINK_EN = true) --
slink_rx_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'L');
slink_rx_src_i : in std_ulogic_vector(3 downto 0) := (others => 'L');
slink_rx_val_i : in std_ulogic := 'L';
slink_rx_lst_i : in std_ulogic := 'L';
slink_rx_rdy_o : out std_ulogic;
slink_tx_dat_o : out std_ulogic_vector(31 downto 0);
slink_tx_dst_o : out std_ulogic_vector(3 downto 0);
slink_tx_val_o : out std_ulogic;
slink_tx_lst_o : out std_ulogic;
slink_tx_rdy_i : in std_ulogic := 'L';
Expand All @@ -855,7 +857,7 @@ package neorv32_package is
spi_clk_o : out std_ulogic;
spi_dat_o : out std_ulogic;
spi_dat_i : in std_ulogic := 'L';
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
spi_csn_o : out std_ulogic_vector(7 downto 0); -- SPI CS
-- SDI (available if IO_SDI_EN = true) --
sdi_clk_i : in std_ulogic := 'L';
sdi_dat_o : out std_ulogic;
Expand Down
35 changes: 20 additions & 15 deletions rtl/core/neorv32_top.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ entity neorv32_top is
xbus_adr_o : out std_ulogic_vector(31 downto 0); -- address
xbus_dat_o : out std_ulogic_vector(31 downto 0); -- write data
xbus_we_o : out std_ulogic; -- read/write
xbus_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
xbus_sel_o : out std_ulogic_vector(3 downto 0); -- byte enable
xbus_stb_o : out std_ulogic; -- strobe
xbus_cyc_o : out std_ulogic; -- valid cycle
xbus_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- read data
Expand All @@ -160,12 +160,14 @@ entity neorv32_top is

-- Stream Link Interface (available if IO_SLINK_EN = true) --
slink_rx_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- RX input data
slink_rx_src_i : in std_ulogic_vector(3 downto 0) := (others => 'L'); -- RX source routing information
slink_rx_val_i : in std_ulogic := 'L'; -- RX valid input
slink_rx_lst_i : in std_ulogic := 'L'; -- last element of stream
slink_rx_lst_i : in std_ulogic := 'L'; --RX last element of stream
slink_rx_rdy_o : out std_ulogic; -- RX ready to receive
slink_tx_dat_o : out std_ulogic_vector(31 downto 0); -- TX output data
slink_tx_dst_o : out std_ulogic_vector(3 downto 0); -- TX destination routing information
slink_tx_val_o : out std_ulogic; -- TX valid output
slink_tx_lst_o : out std_ulogic; -- last element of stream
slink_tx_lst_o : out std_ulogic; -- TX last element of stream
slink_tx_rdy_i : in std_ulogic := 'L'; -- TX ready to send

-- XIP (execute in place via SPI) signals (available if XIP_EN = true) --
Expand Down Expand Up @@ -194,7 +196,7 @@ entity neorv32_top is
spi_clk_o : out std_ulogic; -- SPI serial clock
spi_dat_o : out std_ulogic; -- controller data out, peripheral data in
spi_dat_i : in std_ulogic := 'L'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
spi_csn_o : out std_ulogic_vector(7 downto 0); -- chip-select

-- SDI (available if IO_SDI_EN = true) --
sdi_clk_i : in std_ulogic := 'L'; -- SDI serial clock
Expand Down Expand Up @@ -269,7 +271,7 @@ architecture neorv32_top_rtl of neorv32_top is
-- clock generator --
signal clk_cpu : std_ulogic; -- CPU core clock, can be switched off
signal clk_div, clk_div_ff : std_ulogic_vector(11 downto 0);
signal clk_gen : std_ulogic_vector(07 downto 0);
signal clk_gen : std_ulogic_vector(7 downto 0);
signal clk_gen_en, clk_gen_en_ff : std_ulogic;
--
type cg_en_enum_t is (
Expand Down Expand Up @@ -557,16 +559,16 @@ begin
);

-- fast interrupt requests (FIRQs) --
cpu_firq(00) <= '0'; -- reserved
cpu_firq(01) <= firq(FIRQ_CFS);
cpu_firq(02) <= firq(FIRQ_UART0_RX);
cpu_firq(03) <= firq(FIRQ_UART0_TX);
cpu_firq(04) <= firq(FIRQ_UART1_RX);
cpu_firq(05) <= firq(FIRQ_UART1_TX);
cpu_firq(06) <= firq(FIRQ_SPI);
cpu_firq(07) <= firq(FIRQ_TWI);
cpu_firq(08) <= firq(FIRQ_XIRQ);
cpu_firq(09) <= firq(FIRQ_NEOLED);
cpu_firq(0) <= '0'; -- reserved
cpu_firq(1) <= firq(FIRQ_CFS);
cpu_firq(2) <= firq(FIRQ_UART0_RX);
cpu_firq(3) <= firq(FIRQ_UART0_TX);
cpu_firq(4) <= firq(FIRQ_UART1_RX);
cpu_firq(5) <= firq(FIRQ_UART1_TX);
cpu_firq(6) <= firq(FIRQ_SPI);
cpu_firq(7) <= firq(FIRQ_TWI);
cpu_firq(8) <= firq(FIRQ_XIRQ);
cpu_firq(9) <= firq(FIRQ_NEOLED);
cpu_firq(10) <= firq(FIRQ_DMA);
cpu_firq(11) <= firq(FIRQ_SDI);
cpu_firq(12) <= firq(FIRQ_GPTMR);
Expand Down Expand Up @@ -1522,10 +1524,12 @@ begin
rx_irq_o => firq(FIRQ_SLINK_RX),
tx_irq_o => firq(FIRQ_SLINK_TX),
slink_rx_data_i => slink_rx_dat_i,
slink_rx_src_i => slink_rx_src_i,
slink_rx_valid_i => slink_rx_val_i,
slink_rx_last_i => slink_rx_lst_i,
slink_rx_ready_o => slink_rx_rdy_o,
slink_tx_data_o => slink_tx_dat_o,
slink_tx_dst_o => slink_tx_dst_o,
slink_tx_valid_o => slink_tx_val_o,
slink_tx_last_o => slink_tx_lst_o,
slink_tx_ready_i => slink_tx_rdy_i
Expand All @@ -1539,6 +1543,7 @@ begin
firq(FIRQ_SLINK_TX) <= '0';
slink_rx_rdy_o <= '0';
slink_tx_dat_o <= (others => '0');
slink_tx_dst_o <= (others => '0');
slink_tx_val_o <= '0';
slink_tx_lst_o <= '0';
end generate;
Expand Down
4 changes: 4 additions & 0 deletions rtl/system_integration/neorv32_vivado_ip.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -162,12 +162,14 @@ entity neorv32_vivado_ip is
-- ------------------------------------------------------------
-- Source --
-- s0_axis_aclk : in std_ulogic := '0'; -- just to satisfy Vivado, but not actually used!
s0_axis_tdest : out std_ulogic_vector(3 downto 0);
s0_axis_tvalid : out std_ulogic;
s0_axis_tready : in std_ulogic := '0';
s0_axis_tdata : out std_ulogic_vector(31 downto 0);
s0_axis_tlast : out std_ulogic;
-- Sink --
-- s1_axis_aclk : in std_ulogic := '0'; -- just to satisfy Vivado, but not actually used!
s1_axis_tid : in std_ulogic_vector(3 downto 0) := x"0";
s1_axis_tvalid : in std_ulogic := '0';
s1_axis_tready : out std_ulogic;
s1_axis_tdata : in std_ulogic_vector(31 downto 0) := x"00000000";
Expand Down Expand Up @@ -387,10 +389,12 @@ begin
xbus_err_i => wb_core.err,
-- Stream Link Interface (available if IO_SLINK_EN = true) --
slink_rx_dat_i => s1_axis_tdata,
slink_rx_src_i => s1_axis_tid,
slink_rx_val_i => s1_axis_tvalid,
slink_rx_lst_i => s1_axis_tlast,
slink_rx_rdy_o => s1_axis_tready,
slink_tx_dat_o => s0_axis_tdata,
slink_tx_dst_o => s0_axis_tdest,
slink_tx_val_o => s0_axis_tvalid,
slink_tx_lst_o => s0_axis_tlast,
slink_tx_rdy_i => s0_axis_tready,
Expand Down

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