[rtl] IO: use termination record for rsp bus reset

stnolting · Jun 30, 2024 · 297466f · 297466f
1 parent 24ab047
commit 297466f
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Showing 20 changed files with 74 additions and 119 deletions.
diff --git a/rtl/core/neorv32_cfs.vhd b/rtl/core/neorv32_cfs.vhd
@@ -147,14 +147,11 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      cfs_reg_wr(0)  <= (others => '0');
-      cfs_reg_wr(1)  <= (others => '0');
-      cfs_reg_wr(2)  <= (others => '0');
-      cfs_reg_wr(3)  <= (others => '0');
-      --
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
+      cfs_reg_wr(0) <= (others => '0');
+      cfs_reg_wr(1) <= (others => '0');
+      cfs_reg_wr(2) <= (others => '0');
+      cfs_reg_wr(3) <= (others => '0');
+      bus_rsp_o     <= rsp_terminate_c;
     elsif rising_edge(clk_i) then -- synchronous interface for read and write accesses
       -- transfer/access acknowledge --
       bus_rsp_o.ack <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_crc.vhd b/rtl/core/neorv32_crc.vhd
@@ -54,13 +54,11 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      crc.mode <= (others => '0');
-      crc.poly <= (others => '0');
-      crc.data <= (others => '0');
-      we_ack   <= (others => '0');
+      bus_rsp_o <= rsp_terminate_c;
+      crc.mode  <= (others => '0');
+      crc.poly  <= (others => '0');
+      crc.data  <= (others => '0');
+      we_ack    <= (others => '0');
     elsif rising_edge(clk_i) then
       -- bus handshake --
       bus_rsp_o.data <= (others => '0');

diff --git a/rtl/core/neorv32_debug_dm.vhd b/rtl/core/neorv32_debug_dm.vhd
@@ -641,9 +641,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack     <= '0';
-      bus_rsp_o.err     <= '0';
-      bus_rsp_o.data    <= (others => '0');
+      bus_rsp_o         <= rsp_terminate_c;
       dci.data_reg      <= (others => '0');
       dci.halt_ack      <= '0';
       dci.resume_ack    <= '0';

diff --git a/rtl/core/neorv32_dma.vhd b/rtl/core/neorv32_dma.vhd
@@ -112,9 +112,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack    <= '0';
-      bus_rsp_o.err    <= '0';
-      bus_rsp_o.data   <= (others => '0');
+      bus_rsp_o        <= rsp_terminate_c;
       config.enable    <= '0';
       config.auto      <= '0';
       config.fence     <= '0';

diff --git a/rtl/core/neorv32_gpio.vhd b/rtl/core/neorv32_gpio.vhd
@@ -40,10 +40,8 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      dout           <= (others => '0');
+      bus_rsp_o <= rsp_terminate_c;
+      dout      <= (others => '0');
     elsif rising_edge(clk_i) then
       -- bus handshake --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_gptmr.vhd b/rtl/core/neorv32_gptmr.vhd
@@ -82,14 +82,12 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      ctrl           <= (others => '0');
-      trig_match     <= '0';
-      trig_capture   <= '0';
-      timer.cnt_we   <= '0';
-      timer.thres    <= (others => '0');
+      bus_rsp_o    <= rsp_terminate_c;
+      ctrl         <= (others => '0');
+      trig_match   <= '0';
+      trig_capture <= '0';
+      timer.cnt_we <= '0';
+      timer.thres  <= (others => '0');
     elsif rising_edge(clk_i) then
       -- defaults --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_mtime.vhd b/rtl/core/neorv32_mtime.vhd
@@ -49,16 +49,13 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      mtimecmp_lo    <= (others => '0');
-      mtimecmp_hi    <= (others => '0');
-      mtime_we       <= (others => '0');
-      mtime_lo       <= (others => '0');
-      mtime_lo_cry   <= (others => '0');
-      mtime_hi       <= (others => '0');
-      --
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
+      mtimecmp_lo  <= (others => '0');
+      mtimecmp_hi  <= (others => '0');
+      mtime_we     <= (others => '0');
+      mtime_lo     <= (others => '0');
+      mtime_lo_cry <= (others => '0');
+      mtime_hi     <= (others => '0');
+      bus_rsp_o    <= rsp_terminate_c;
     elsif rising_edge(clk_i) then
       -- mtimecmp --
       if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(3) = '1') then

diff --git a/rtl/core/neorv32_neoled.vhd b/rtl/core/neorv32_neoled.vhd
@@ -123,18 +123,15 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      ctrl.enable    <= '0';
-      ctrl.mode      <= '0';
-      ctrl.strobe    <= '0';
-      ctrl.clk_prsc  <= (others => '0');
-      ctrl.irq_conf  <= '0';
-      ctrl.t_total   <= (others => '0');
-      ctrl.t0_high   <= (others => '0');
-      ctrl.t1_high   <= (others => '0');
-      --
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
+      ctrl.enable   <= '0';
+      ctrl.mode     <= '0';
+      ctrl.strobe   <= '0';
+      ctrl.clk_prsc <= (others => '0');
+      ctrl.irq_conf <= '0';
+      ctrl.t_total  <= (others => '0');
+      ctrl.t0_high  <= (others => '0');
+      ctrl.t1_high  <= (others => '0');
+      bus_rsp_o     <= rsp_terminate_c;
     elsif rising_edge(clk_i) then
       -- bus handshake --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_onewire.vhd b/rtl/core/neorv32_onewire.vhd
@@ -104,9 +104,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
+      bus_rsp_o      <= rsp_terminate_c;
       ctrl.enable    <= '0';
       ctrl.clk_prsc  <= (others => '0');
       ctrl.clk_div   <= (others => '0');

diff --git a/rtl/core/neorv32_pwm.vhd b/rtl/core/neorv32_pwm.vhd
@@ -60,12 +60,10 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      enable         <= '0';
-      prsc           <= (others => '0');
-      pwm_ch         <= (others => (others => '0'));
+      bus_rsp_o <= rsp_terminate_c;
+      enable    <= '0';
+      prsc      <= (others => '0');
+      pwm_ch    <= (others => (others => '0'));
     elsif rising_edge(clk_i) then
       -- bus handshake --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_sdi.vhd b/rtl/core/neorv32_sdi.vhd
@@ -111,9 +111,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack     <= '0';
-      bus_rsp_o.err     <= '0';
-      bus_rsp_o.data    <= (others => '0');
+      bus_rsp_o         <= rsp_terminate_c;
       ctrl.enable       <= '0';
       ctrl.clr_rx       <= '0';
       ctrl.irq_rx_avail <= '0';

diff --git a/rtl/core/neorv32_slink.vhd b/rtl/core/neorv32_slink.vhd
@@ -115,9 +115,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack      <= '0';
-      bus_rsp_o.err      <= '0';
-      bus_rsp_o.data     <= (others => '0');
+      bus_rsp_o          <= rsp_terminate_c;
       ctrl.enable        <= '0';
       ctrl.rx_clr        <= '0';
       ctrl.tx_clr        <= '0';

diff --git a/rtl/core/neorv32_spi.vhd b/rtl/core/neorv32_spi.vhd
@@ -121,9 +121,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack     <= '0';
-      bus_rsp_o.err     <= '0';
-      bus_rsp_o.data    <= (others => '0');
+      bus_rsp_o         <= rsp_terminate_c;
       ctrl.enable       <= '0';
       ctrl.cpha         <= '0';
       ctrl.cpol         <= '0';

diff --git a/rtl/core/neorv32_sysinfo.vhd b/rtl/core/neorv32_sysinfo.vhd
@@ -145,13 +145,9 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
+      bus_rsp_o <= rsp_terminate_c;
     elsif rising_edge(clk_i) then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
+      bus_rsp_o <= rsp_terminate_c; -- default
       if (bus_req_i.stb = '1') and (bus_req_i.rw = '0') then -- read-only
         bus_rsp_o.ack  <= '1';
         bus_rsp_o.data <= sysinfo(to_integer(unsigned(bus_req_i.addr(3 downto 2))));

diff --git a/rtl/core/neorv32_trng.vhd b/rtl/core/neorv32_trng.vhd
@@ -92,12 +92,10 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack   <= '0';
-      bus_rsp_o.err   <= '0';
-      bus_rsp_o.data  <= (others => '0');
-      fifo_clr        <= '0';
-      irq_sel         <= '0';
-      enable          <= '0';
+      bus_rsp_o <= rsp_terminate_c;
+      fifo_clr  <= '0';
+      irq_sel   <= '0';
+      enable    <= '0';
     elsif rising_edge(clk_i) then
       -- defaults --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_twi.vhd b/rtl/core/neorv32_twi.vhd
@@ -120,12 +120,10 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      ctrl.enable    <= '0';
-      ctrl.prsc      <= (others => '0');
-      ctrl.cdiv      <= (others => '0');
+      bus_rsp_o   <= rsp_terminate_c;
+      ctrl.enable <= '0';
+      ctrl.prsc   <= (others => '0');
+      ctrl.cdiv   <= (others => '0');
     elsif rising_edge(clk_i) then
       -- bus handshake defaults --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_uart.vhd b/rtl/core/neorv32_uart.vhd
@@ -148,9 +148,7 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack      <= '0';
-      bus_rsp_o.err      <= '0';
-      bus_rsp_o.data     <= (others => '0');
+      bus_rsp_o          <= rsp_terminate_c;
       ctrl.enable        <= '0';
       ctrl.sim_mode      <= '0';
       ctrl.hwfc_en       <= '0';

diff --git a/rtl/core/neorv32_wdt.vhd b/rtl/core/neorv32_wdt.vhd
@@ -79,17 +79,15 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      ctrl.enable    <= '0'; -- disable WDT after reset
-      ctrl.lock      <= '0'; -- unlock after reset
-      ctrl.dben      <= '0';
-      ctrl.sen       <= '0';
-      ctrl.strict    <= '0';
-      ctrl.timeout   <= (others => '0');
-      reset_wdt      <= '0';
-      reset_force    <= '0';
+      bus_rsp_o    <= rsp_terminate_c;
+      ctrl.enable  <= '0'; -- disable WDT after reset
+      ctrl.lock    <= '0'; -- unlock after reset
+      ctrl.dben    <= '0';
+      ctrl.sen     <= '0';
+      ctrl.strict  <= '0';
+      ctrl.timeout <= (others => '0');
+      reset_wdt    <= '0';
+      reset_force  <= '0';
     elsif rising_edge(clk_i) then
       -- bus handshake --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_xip.vhd b/rtl/core/neorv32_xip.vhd
@@ -135,13 +135,11 @@ begin
   ctrl_bus_access : process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      ctrl           <= (others => '0');
-      spi_data_lo    <= (others => '0');
-      spi_data_hi    <= (others => '0');
-      spi_trigger    <= '0';
+      bus_rsp_o   <= rsp_terminate_c;
+      ctrl        <= (others => '0');
+      spi_data_lo <= (others => '0');
+      spi_data_hi <= (others => '0');
+      spi_trigger <= '0';
     elsif rising_edge(clk_i) then
       -- bus handshake --
       bus_rsp_o.ack  <= bus_req_i.stb;

diff --git a/rtl/core/neorv32_xirq.vhd b/rtl/core/neorv32_xirq.vhd
@@ -64,13 +64,11 @@ begin
   bus_access: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
-      bus_rsp_o.ack  <= '0';
-      bus_rsp_o.err  <= '0';
-      bus_rsp_o.data <= (others => '0');
-      nclr_pending   <= (others => '0');
-      irq_type       <= (others => '0');
-      irq_polarity   <= (others => '0');
-      irq_enable     <= (others => '0');
+      bus_rsp_o    <= rsp_terminate_c;
+      nclr_pending <= (others => '0');
+      irq_type     <= (others => '0');
+      irq_polarity <= (others => '0');
+      irq_enable   <= (others => '0');
     elsif rising_edge(clk_i) then
       -- defaults --
       bus_rsp_o.ack  <= bus_req_i.stb;