Merge pull request #283 from stnolting/fix_pmpaddr_bug

🐛 [PMP] fix pmpaddr CSR layout

CHANGELOG.md

@@ -33,6 +33,7 @@ The version number is globally defined by the `hw_version_c` constant in the mai
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:----------:|:-------:|:--------|
+| 02.03.2022 | 1.6.8.8 | :bug: fixed bug in layout of CPU's `pmpaddr` CSRs (**physical memory protection**); [PR #283](https://github.com/stnolting/neorv32/pull/283) |
 | 01.03.2022 | 1.6.8.7 | minor optimizations, code clean-ups and edits |
 | 26.02.2022 | 1.6.8.6 | :warning: :lock: **reworked Physical Memory Protection (PMP)**: replacing `NAPOT` mode by `TOR` mode and fixing several minor PMP CSR-access bugs; maximum number of PMP regions is now limited to 16 entries; :warning: removed **BUSKEEPER's NULL address check** (introduced in version `1.6.5.4`) - use a single PMP entry instead; see [PR #281](https://github.com/stnolting/neorv32/pull/281) |
 | 25.02.2022 | 1.6.8.5 | minor BUSMUX (bus multiplexer for CPU's instruction and data buses) and CPU control edits (pipeline front-end) |

docs/datasheet/cpu_csr.adoc

@@ -478,19 +478,19 @@ interrupt-triggering processor module.
 
 The available physical memory protection logic is configured via the <<_pmp_num_regions>> and
 <<_pmp_min_granularity>> top entity generics. <<_pmp_num_regions>> defines the number of implemented
-protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
+protection regions and thus, the implementation of the available _PMP entries_. Each PMP entry consists of an
+8-bit `pmpcfg` CSR entry and a complete `pmpaddr*` CSR.
 See section <<_pmp_physical_memory_protection>> for more information.
 
 [NOTE]
-
 If trying to access an PMP-related CSR beyond <<_pmp_num_regions>> **no illegal instruction
 exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
-However, any access beyond `pmpcfg3` or `pmpaddr15` (if <<_pmp_num_regions>> is 16, which is the maximum
-value) will raise an illegal instruction exception.
+However, any access beyond `pmpcfg3` or `pmpaddr15`, which are the last physically implemented registers if
+<<_pmp_num_regions>> == 16, will raise an illegal instruction exception as these CSRs are not implemented at all.
 
 
 :sectnums!:
-===== **`neorv32_cpu_pmp_get_num_regions`**
+===== **`pmpcfg`**
 
 [cols="4,27,>7"]
 [frame="topbot",grid="none"]
@@ -502,7 +502,7 @@ regions, where each `pmpcfg*` CSR provides configuration bits for four regions (
 The actual number of available `pmpcfg` CSRs and CSR entries is defined by the <<_pmp_num_regions>> generic.
 |=======================
 
-.Physical memory protection configuration register entry (1 out of 4)
+.Physical memory protection configuration register layout (1 entry out of 4)
 [cols="^1,^3,^1,<11"]
 [options="header",grid="rows"]
 |=======================
@@ -515,6 +515,9 @@ The actual number of available `pmpcfg` CSRs and CSR entries is defined by the <
 | 0   | `R` | r/w | read permission
 |=======================
 
+[WARNING]
+Setting the lock bit `L` **only locks the according PMP entry** and not the PMP entries below!
+
 
 :sectnums!:
 ===== **`pmpaddr`**
@@ -524,9 +527,18 @@ The actual number of available `pmpcfg` CSRs and CSR entries is defined by the <
 |=======================
 | 0x3b0 - 0x3bf| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr15`
 3+| Reset value: _UNDEFINED_
-3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
-address and the region size. Note that the the two LSBs (`1:0`) of each `pmpaddr` register are hardwired to zero. Hence, the minimal
-region size is 4 bytes. The actual number of available `pmpaddr` CSRs is defined by the <<_pmp_num_regions>> generic.
+3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure bits 33:2 of the PMP region's
+physical memory address. The actual number of available `pmpaddr` CSRs is defined by the <<_pmp_num_regions>> generic.
+|=======================
+
+.Physical memory protection address register layout
+[cols="^6,^3,<7"]
+[options="header",grid="rows"]
+|=======================
+| Bit                                | R/W | Function
+| 31:30                              | r/- | Hardwired to zero
+| 29 : _log2(PMP_MIN_GRANULARITY)-2_ | r/w | Bits 31 downto _log2(PMP_MIN_GRANULARITY)_ of the region's address
+| _log2(PMP_MIN_GRANULARITY)-2_ : 0  | r/- | Hardwired to zero
 |=======================
 
 [NOTE]

docs/datasheet/soc.adoc

@@ -1247,43 +1247,6 @@ applications - even if the bootloader or all IO devices are not implemented - wi
 hardware sources.
 
 
-:sectnums:
-==== Physical Memory Attributes
-
-The processor setup defines fixed attributes for the four processor-internal address space regions.
-Accessing a memory region in a way that violates any of these attributes will raise an according
-access exception..
-
-* `r` - read access (from CPU data access interface, "loads")
-* `w` - write access (from CPU data access interface, "stores")
-* `x` - execute access (from CPU instruction fetch interface)
-* `a` - atomic access (from CPU data access interface)
-* `8` - byte (8-bit)-accessible (when writing)
-* `16` - half-word (16-bit)-accessible (when writing)
-* `32` - word (32-bit)-accessible (when writing)
-
-[NOTE]
-Read accesses (loads and instruction fetches) can always access data in
-word, half-word (for instruction fetch only if `C` extension is enabled)
-and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
-
-[TIP]
-The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
-Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
-provided using the RISC-V <<_machine_physical_memory_protection_csrs>>.
-
-[cols="^1,^2,^2,^3,^2"]
-[options="header",grid="rows"]
-|=======================
-| # | Region                | Base address | Size        | Attributes
-| 5 | IO/peripheral devices | 0xfffffe00   | 512 bytes   | `r/w/a/32`
-| 4 | On-chip debugger      | 0xfffff800   | 512 bytes   | `r/w/x/32`
-| 3 | Bootloader ROM        | 0xffff0000   | up to 32kB  | `r/x/a`
-| 2 | DMEM                  | 0x80000000   | up to "2GB" | `r/w/x/a/8/16/32`
-| 1 | IMEM                  | 0x00000000   | up to 2GB   | `r/w/x/a/8/16/32`
-|=======================
-
-
 :sectnums:
 ==== Memory Configuration