⚠️ rework CFU interface (#932)

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 29.06.2024 | 1.10.0.5 | :warning: rework and optimize custom functions unit (CFU) interface; simplified illegal RVC decoding | [#932](https://github.com/stnolting/neorv32/pull/932) |
 | 23.06.2024 | 1.10.0.4 | minor rtl edits/cleanups | [#931](https://github.com/stnolting/neorv32/pull/931) |
 | 22.06.2024 | 1.10.0.3 | UARTs: add flags to clear RX/TX FIFOs; DMA: add FIRQ trigger type configuration flag | [#930](https://github.com/stnolting/neorv32/pull/930) |
 | 21.06.2024 | 1.10.0.2 | minor code rtl clean-ups; fix some missing TOP defaults | [#929](https://github.com/stnolting/neorv32/pull/929) |

docs/datasheet/cpu_csr.adoc

@@ -476,7 +476,8 @@ However, any write-access will be ignored and will not cause an exception to mai
 The RISC-V priv. spec. suggests that the instruction word written to `mtinst` by the hardware should be "transformed".
 However, the NEORV32 `mtinst` CSR uses a simplified transformation scheme: if the trap-causing instruction is a
 standard 32-bit instruction, `mtinst` contains the exact instruction word that caused the trap. If the trap-causing
-instruction is a compressed instruction, `mtinst` contains the de-compressed 32-bit equivalent with bit 1 being cleared.
+instruction is a compressed instruction, `mtinst` contains the de-compressed 32-bit equivalent with bit 1 being cleared
+while all remaining bits represent the pre-decoded 32-bit instruction equivalent.
 
 
 

rtl/core/neorv32_cpu_alu.vhd

@@ -81,6 +81,12 @@ architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
   signal fpu_csr_we, cfu_csr_we : std_ulogic;
   signal fpu_csr_rd, cfu_csr_rd : std_ulogic_vector(XLEN-1 downto 0);
 
+  -- CFU proxy --
+  signal cfu_run  : std_ulogic;
+  signal cfu_done : std_ulogic;
+  signal cfu_wait : std_ulogic_vector(1 downto 0);
+  signal cfu_res  : std_ulogic_vector(XLEN-1 downto 0);
+
   -- CSR read-backs --
   signal csr_rdata_fpu, csr_rdata_cfu : std_ulogic_vector(XLEN-1 downto 0);
 
@@ -287,29 +293,52 @@ begin
     neorv32_cpu_cp_cfu_inst: entity neorv32.neorv32_cpu_cp_cfu
     port map (
       -- global control --
-      clk_i   => clk_i,                      -- global clock, rising edge
-      rstn_i  => rstn_i,                     -- global reset, low-active, async
-      ctrl_i  => ctrl_i,                     -- main control bus
-      start_i => cp_start(4),                -- trigger operation
+      clk_i       => clk_i,                          -- global clock, rising edge
+      rstn_i      => rstn_i,                         -- global reset, low-active, async
+      -- operation control --
+      start_i     => cp_start(4),                    -- operation trigger/strobe
+      active_i    => cfu_run,                        -- operation in progress
+      rtype_i     => ctrl_i.ir_opcode(6 downto 5),   -- instruction type, see constants below
+      funct3_i    => ctrl_i.ir_funct3,               -- "funct3" bit-field from custom instruction word
+      funct7_i    => ctrl_i.ir_funct12(11 downto 5), -- "funct7" bit-field from custom instruction word
       -- CSR interface --
-      csr_we_i    => cfu_csr_we,             -- write enable
-      csr_addr_i  => csr_addr_i(1 downto 0), -- address
-      csr_wdata_i => csr_wdata_i,            -- write data
-      csr_rdata_o => cfu_csr_rd,             -- read data
-      -- data input --
-      rs1_i   => rs1_i,                      -- rf source 1
-      rs2_i   => rs2_i,                      -- rf source 2
-      rs3_i   => rs3_i,                      -- rf source 3
-      rs4_i   => rs4_i,                      -- rf source 4
+      csr_we_i    => cfu_csr_we,                     -- write enable
+      csr_addr_i  => csr_addr_i(1 downto 0),         -- address
+      csr_wdata_i => csr_wdata_i,                    -- write data
+      csr_rdata_o => cfu_csr_rd,                     -- read data
+      -- operands --
+      rs1_i       => rs1_i,                          -- rf source 1
+      rs2_i       => rs2_i,                          -- rf source 2
+      rs3_i       => rs3_i,                          -- rf source 3
+      rs4_i       => rs4_i,                          -- rf source 4
       -- result and status --
-      res_o   => cp_result(4),               -- operation result
-      valid_o => cp_valid(4)                 -- data output valid
+      result_o    => cfu_res,                        -- operation result
+      valid_o     => cfu_done                        -- data output valid (one cycle ahead); operation done
     );
 
     -- CSR proxy --
     cfu_csr_en    <= '1' when (csr_addr_i(11 downto 2) = csr_cfureg0_c(11 downto 2)) else '0';
     cfu_csr_we    <= cfu_csr_en and csr_we_i;
     csr_rdata_cfu <= cfu_csr_rd when (cfu_csr_en = '1') else (others => '0');
+
+    -- operation proxy --
+    cfu_arbiter: process(rstn_i, clk_i)
+    begin
+      if (rstn_i = '0') then
+        cfu_wait <= (others => '0');
+      elsif rising_edge(clk_i) then
+        cfu_wait(1) <= cfu_wait(0); -- shift register
+        if (cfu_wait(0) = '0') then -- CFU is idle
+          cfu_wait(0) <= cp_start(4); -- trigger new CFU operation
+        elsif (cfu_done = '1') or (ctrl_i.cpu_trap = '1') then -- operation done or abort if trap (exception)
+          cfu_wait(0) <= '0';
+        end if;
+      end if;
+    end process cfu_arbiter;
+
+    cfu_run      <= cp_start(4) or cfu_wait(0); -- CFU operation in progress
+    cp_result(4) <= cfu_res when (cfu_wait(1) = '1') else (others => '0'); -- output gate
+    cp_valid(4)  <= cfu_wait(0) and cfu_done;
   end generate;
 
   neorv32_cpu_cp_cfu_inst_false:

rtl/core/neorv32_cpu_control.vhd

@@ -432,8 +432,8 @@ begin
   if CPU_EXTENSION_RISCV_C generate
     neorv32_cpu_decompressor_inst: entity neorv32.neorv32_cpu_decompressor
     port map (
-      ci_instr16_i => issue_engine.ci_i16,
-      ci_instr32_o => issue_engine.ci_i32
+      instr16_i => issue_engine.ci_i16,
+      instr32_o => issue_engine.ci_i32
     );
   end generate;