Merge pull request #98 from stnolting/dependabot/submodules/neorv32-8… · stnolting/neorv32-verilog@4bd2c15

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Merge pull request #98 from stnolting/dependabot/submodules/neorv32-8…

…9d0f9d

[Dependabot]: Bump neorv32 from `c5dd617` to `89d0f9d`

stnolting committed Jun 3, 2024

2 parents 37b1ba8 + 101de75 commit 4bd2c15

neorv32

Submodule neorv32 updated 39 files

+4 −0		CHANGELOG.md
+5 −7		README.md
+25 −28		docs/datasheet/overview.adoc
+12 −16		docs/datasheet/soc.adoc
+3 −1		docs/datasheet/soc_dcache.adoc
+3 −1		docs/datasheet/soc_icache.adoc
+19 −5		docs/datasheet/soc_xbus.adoc
+56 −39		docs/datasheet/soc_xirq.adoc
+ −		docs/figures/neorv32_bus.png
+ −		docs/figures/neorv32_logo_riscv_small.png
+ −		docs/figures/vivado_ip_soc.png
+4 −3		docs/legal.adoc
+ −		docs/references/bitmanip-draft.pdf
+ −		docs/references/riscv-privileged.pdf
+ −		docs/references/riscv-spec.pdf
+ −		docs/references/riscv-unprivileged.pdf
+ −		docs/references/riscv-zicond_1.0.1.pdf
+1 −1		docs/userguide/packaging_vivado.adoc
+5 −1		rtl/README.md
+45 −112		rtl/core/neorv32_cache.vhd
+3 −8		rtl/core/neorv32_gpio.vhd
+11 −10		rtl/core/neorv32_intercon.vhd
+26 −3		rtl/core/neorv32_package.vhd
+21 −21		rtl/core/neorv32_top.vhd
+2 −0		rtl/core/neorv32_xbus.vhd
+10 −33		rtl/core/neorv32_xip.vhd
+31 −20		rtl/core/neorv32_xirq.vhd
+15 −0		rtl/cpu_hdl_files.f
+48 −0		rtl/processor_hdl_files.f
+35 −38		rtl/system_integration/neorv32_vivado_ip.tcl
+81 −48		rtl/system_integration/neorv32_vivado_ip.vhd
+1 −2		sim/neorv32_tb.vhd
+1 −2		sim/simple/neorv32_tb.simple.vhd
+8 −1		sw/example/demo_xirq/main.c
+2 −4		sw/example/processor_check/main.c
+0 −13		sw/lib/include/neorv32_cpu.h
+20 −4		sw/lib/include/neorv32_xirq.h
+29 −0		sw/lib/source/neorv32_xirq.c
+11 −1		sw/svd/neorv32.svd

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