-
Notifications
You must be signed in to change notification settings - Fork 16
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
UPduino Radiant project stale #173
Comments
Oh right, that seems to be outdated. I'll update that. |
Setup is updated and should be working now 😉 |
Synth worked on first attempt. Map did also. PnR failed on first attempt. Increased iterations to 10. 3 failures 7 successes. Looks like some seeds will fail.
Successful bitfile generation. Used: Radiant 2022.1.1.289.4/Symplify Pro S-2021.09LR-SP2. Thank you very much for the quick response. Now onto using it to learn about RISC-V! |
I've also encountered that issue... I'm not sure where that is coming from. Anyway, good to hear your setup works now! 👍 |
The project appears to be missing the wishbone file.
Reversion to commit in March 2024 around the time of last update also fails to synthesis against the head here. Errors occur at generate statements in generic processor HDL (neorv32_top.vhd).
Radiant 2022.1.1.289.4/Symplify Pro S-2021.09LR-SP2
The text was updated successfully, but these errors were encountered: