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[radiant] update project sources + demo bitstream
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@stnolting
stnolting committed Mar 15, 2024
1 parent 818e339 commit 648e4d3
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Showing 2 changed files with 50 additions and 47 deletions.
97 changes: 50 additions & 47 deletions radiant/iCEBreaker/iCEBreaker.rdf
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Original file line number Diff line number Diff line change
Expand Up @@ -3,145 +3,145 @@
<Options/>
<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="icebreaker_top" top="icebreaker_top"/>
<Source name="../../../neorv32/rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_package.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_boot_rom.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_bootloader_image.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_bootloader_image.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cfs.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_boot_rom.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_clockgate.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cfs.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_alu.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_clockgate.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_control.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_alu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_control.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_cp_cond.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_cp_cond.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_lsu.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_pmp.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_lsu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_crc.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_pmp.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_dcache.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_crc.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_debug_dtm.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_dcache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_dma.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_dmem.entity.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_debug_dtm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_dma.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_gpio.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_dmem.entity.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_gptmr.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_gpio.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_icache.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_gptmr.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_icache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_intercon.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_mtime.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_intercon.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_neoled.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_mtime.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_onewire.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_neoled.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_package.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_onewire.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_pwm.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_pwm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_sdi.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_sdi.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_slink.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_slink.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_spi.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_spi.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_sysinfo.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_sysinfo.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_trng.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_trng.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_twi.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_twi.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_uart.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_uart.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_wdt.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_wdt.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_xip.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_wishbone.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_xirq.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_xip.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_cache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../neorv32/rtl/core/neorv32_xirq.vhd" type="VHDL" type_short="VHDL">
<Source name="../../neorv32/rtl/core/neorv32_xbus.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="neorv32_dmem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
Expand All @@ -150,6 +150,9 @@
<Source name="neorv32_imem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
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Binary file modified radiant/iCEBreaker/impl_1/iCEBreaker_impl_1.bin
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