[radiant] update UPduino setup

#143 make sure to use Radiant v2022.1
stnolting · Feb 11, 2024 · 5e0c7df · 5e0c7df
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diff --git a/radiant/UPduino_v3/.gitignore b/radiant/UPduino_v3/.gitignore
@@ -3,13 +3,6 @@
 !.gitignore
 !README.md
 
-!system_pll/
-system_pll/*
-!system_pll/system_pll.ipx
-!system_pll/rtl/
-system_pll/rtl/*
-!system_pll/rtl/system_pll.v
-
 !source/
 source/*
 !source/impl_1.xcf

diff --git a/radiant/UPduino_v3/README.md b/radiant/UPduino_v3/README.md
@@ -1,34 +1,27 @@
 # NEORV32 Example Setup for the tinyVision.ai Inc. "UPduino v3.0" FPGA Board
 
+:warning: This setup _requires_ Lattice Radiant version **2022.1**!
 
-This example setup turns the UPduino v3.0 board, which features a Lattice iCE40 UltraPlus FPGA, into a medium-scale NEORV32 *microcontroller*.
+This example setup turns the UPduino v3.0 board, which features a Lattice iCE40 UltraPlus FPGA, into a tiny-scale NEORV32 microcontroller.
 The processor setup provides 64kB of data and instruction memory, an RTOS-capable CPU (privileged architecture)
 and a set of standard peripherals like UART, TWI and SPI.
 
-
 * FPGA Board: :books: [tinyVision.ai Inc. UPduino v3 FPGA Board (GitHub)](https://github.com/tinyvision-ai-inc/UPduino-v3.0/),
 :credit_card: buy on [Tindie](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/)
 * FPGA: Lattice iCE40 UltraPlus 5k `iCE40UP5K-SG48I`
-* Toolchain: Lattice Radiant (tested with Radiant version 3.0.0), using *Lattice Synthesis Engine (LSE)*
-* Top entity: [`neorv32_upduino_v3_top.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3_top.vhd) (instantiates NEORV32 top entity)
+* Toolchain: Lattice Radiant (tested with version 2022.1), using **Synplify Pro** synthesis engine
+* Top entity: `neorv32_upduino_v3_top.vhd`
 
 
 ### Processor Configuration
 
-- [x] NEORV32 version: v1.9.3.9
-- [x] CPU: `rv32imacu_Zicsr_Zicntr` (reduced CPU `[m]instret` & `[m]cycle` counter width!)
-- [x] Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM
-- [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`
-- [x] Clock: 21 MHz from on-chip HF oscillator (via PLL)
-- [x] Reset: via PLL "locked" signal; external "reset" via FPGA re-reconfiguration pin (`creset_n`)
-- [x] Tested with processor version [`1.6.1.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
-- [x] On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader)
-
-:information_source: This setup uses optimized platform-specific memory modules for the internal data and instruction memories (DMEM & IMEM). Each memory uses two
-UltraPlus SPRAM primitives (total memory size per memory = 2 x 32kB = 64kB). VHDL source file for platform-specific IMEM:
-[`neorv32_imem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_imem.ice40up_spram.vhd);
-VHDL source file for platform-specific DMEM: [`neorv32_dmem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_dmem.ice40up_spram.vhd).
-These platform-specific memories are used *instead* of the default platform-agnostic modules from the core's `rtl/core/mem` folder.
+* CPU: `rv32imcu_Zicsr_Zicntr`
+* Memory: 64kB instruction memory (internal IMEM), 64kB data memory (internal DMEM), 4kB bootloader ROM
+* Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`
+* Clock: 24 MHz from on-chip HF oscillator
+* Reset: indirect reset via FPGA re-reconfiguration pin (`creset_n`)
+* Tested with processor version [`1.9.4.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
+* On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader)
 
 
 ### Interface Signals
@@ -68,26 +61,6 @@ for the FPGA pin mapping.
 GPIO output 0 (`gpio_o(0)`, also connected to the RGB drive) is used as output for a high-active **status LED** driven by the bootloader.
 
 
-### FPGA Utilization
-
-```
-Number of slice registers: 1754 out of 5280  (33%)
-Number of I/O registers:     11 out of  117   (9%)
-Number of LUT4s:           4882 out of 5280  (92%)
-Number of DSPs:               0 out of    8   (0%)
-Number of I2Cs:               0 out of    2   (0%)
-Number of High Speed OSCs:    1 out of    1 (100%)
-Number of Low Speed OSCs:     0 out of    1   (0%)
-Number of RGB PWM:            0 out of    1   (0%)
-Number of RGB Drivers:        1 out of    1 (100%)
-Number of SCL FILTERs:        0 out of    2   (0%)
-Number of SRAMs:              4 out of    4 (100%)
-Number of WARMBOOTs:          0 out of    1   (0%)
-Number of SPIs:               0 out of    2   (0%)
-Number of EBRs:              15 out of   30  (50%)
-Number of PLLs:               1 out of    1 (100%)
-```
-
 ### FPGA Setup
 
 1. start Lattice Radiant (in GUI mode)
@@ -101,4 +74,3 @@ you can use the pre-build configuration `source/impl_1.xcf`
 8. select "W25Q32" under "SPI Flash Options / Device"
 9. close the dialog by clicking "ok"
 10. click on "Program Device"
-
diff --git a/radiant/UPduino_v3/neorv32_upduino_v3.rdf b/radiant/UPduino_v3/neorv32_upduino_v3.rdf
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<RadiantProject version="4.2" radiant="2023.2.0.38.1" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
+<RadiantProject version="4.2" radiant="2022.1.0.52.3" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
     <Options/>
-    <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
+    <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
         <Options def_top="neorv32_upduino_v3_top"/>
         <Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
             <Options lib="work" top_module="neorv32_upduino_v3_top"/>
@@ -153,9 +153,6 @@
         <Source name="../../neorv32/rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
         <Source name="neorv32_upduino_v3.pdc" type="Physical Constraints File" type_short="PDC">
             <Options/>
         </Source>

diff --git a/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd b/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd
@@ -74,24 +74,13 @@ end neorv32_upduino_v3_top;
 architecture neorv32_upduino_v3_top_rtl of neorv32_upduino_v3_top is
 
   -- configuration --
-  constant f_clock_c : natural := 21000000; -- PLL output clock frequency in Hz
+  constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz
 
   -- On-chip oscillator --
   signal hf_osc_clk : std_logic;
 
-  -- PLL (macro generated by radiant) --
-  component system_pll
-  port (
-    ref_clk_i   : in  std_logic;
-    rst_n_i     : in  std_logic;
-    lock_o      : out std_logic;
-    outcore_o   : out std_logic;
-    outglobal_o : out std_logic
-  );
-  end component;
-
-  signal pll_rstn : std_logic;
-  signal pll_clk  : std_logic;
+  -- reset generator --
+  signal rst_cnt : std_ulogic_vector(9 downto 0) := (others => '0'); -- reset by bistream
 
   -- CPU --
   signal cpu_clk  : std_ulogic;
@@ -127,20 +116,21 @@ begin
     CLKHF   => hf_osc_clk
   );
 
+  cpu_clk  <= std_ulogic(hf_osc_clk);
 
-  -- System PLL -----------------------------------------------------------------------------
-  -- -------------------------------------------------------------------------------------------
-  system_pll_inst: system_pll
-  port map (
-    ref_clk_i   => hf_osc_clk,
-    rst_n_i     => '1',
-    lock_o      => pll_rstn,
-    outcore_o   => open,
-    outglobal_o => pll_clk
-  );
 
-  cpu_clk  <= std_ulogic(pll_clk);
-  cpu_rstn <= std_ulogic(pll_rstn);
+  -- Reset Generator ------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  reset_gen: process(cpu_clk)
+  begin
+    if rising_edge(cpu_clk) then
+      if (rst_cnt(9) = '0') then
+        rst_cnt <= std_ulogic_vector(unsigned(rst_cnt) + 1);
+      end if;
+    end if;
+  end process reset_gen;
+
+  cpu_rstn <= rst_cnt(9);
 
 
   -- The core of the problem ----------------------------------------------------------------

diff --git a/radiant/UPduino_v3/source/impl_1.xcf b/radiant/UPduino_v3/source/impl_1.xcf
@@ -1,6 +1,6 @@
 <?xml version='1.0' encoding='utf-8' ?>
 <!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
-<ispXCF version="R3.0">
+<ispXCF version="R2022.1">
 	<Comment></Comment>
 	<Chain>
 		<Comm>SPI</Comm>
@@ -18,7 +18,7 @@
 				<BScanVal>0</BScanVal>
 			</Bypass>
 			<File>../../impl_1/neorv32_upduino_v3_impl_1.bin</File>
-			<FileTime>11/04/21 21:44:40</FileTime>
+			<FileTime>02/11/24 09:39:36</FileTime>
 			<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
@@ -102,7 +102,7 @@
 	</ProjectOptions>
 	<CableOptions>
 		<CableName>USB2</CableName>
-		<PortAdd>FTUSB-1</PortAdd>
-		<USBID>UPduino v3.0 Location 0002 Serial </USBID>
+		<PortAdd>FTUSB-0</PortAdd>
+		<USBID>Single RS232-HS Location 0000 Serial </USBID>
 	</CableOptions>
 </ispXCF>