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Merge pull request #157 from stnolting/dependabot/submodules/neorv32-…
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[Dependabot]: Bump neorv32 from `bd4fb29` to `082146d`
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@stnolting
stnolting committed Mar 17, 2024
2 parents 832b209 + f512615 commit 07c01e6
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Showing 5 changed files with 5 additions and 15 deletions.
2 changes: 1 addition & 1 deletion neorv32
Submodule neorv32 updated 44 files
+6 −4 CHANGELOG.md
+14 −13 CODE_OF_CONDUCT.md
+5 −4 CONTRIBUTING.md
+7 −5 README.md
+6 −21 docs/README.md
+9 −7 docs/datasheet/cpu.adoc
+3 −3 docs/datasheet/cpu_csr.adoc
+1 −1 docs/datasheet/on_chip_debugger.adoc
+0 −2 docs/datasheet/overview.adoc
+7 −9 docs/datasheet/soc.adoc
+11 −18 docs/datasheet/soc_dcache.adoc
+1 −1 docs/datasheet/soc_dma.adoc
+13 −23 docs/datasheet/soc_icache.adoc
+37 −36 docs/datasheet/soc_sysinfo.adoc
+5 −13 docs/datasheet/soc_xbus.adoc
+12 −12 docs/datasheet/soc_xip.adoc
+13 −9 docs/datasheet/software.adoc
+16 −35 docs/figures/license.md
+ − docs/figures/neorv32_bus.png
+8 −12 rtl/README.md
+8 −8 rtl/core/neorv32_bootloader_image.vhd
+150 −83 rtl/core/neorv32_cache.vhd
+5 −5 rtl/core/neorv32_cpu.vhd
+0 −551 rtl/core/neorv32_dcache.vhd
+0 −561 rtl/core/neorv32_icache.vhd
+3 −6 rtl/core/neorv32_package.vhd
+62 −56 rtl/core/neorv32_sysinfo.vhd
+145 −121 rtl/core/neorv32_top.vhd
+16 −27 rtl/core/neorv32_xbus.vhd
+13 −342 rtl/core/neorv32_xip.vhd
+2 −5 rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
+2 −5 rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
+23 −39 rtl/system_integration/neorv32_litex_core_complex.vhd
+6 −4 sim/README.md
+1 −2 sim/neorv32_tb.vhd
+5 −7 sim/simple/neorv32_tb.simple.vhd
+10 −27 sw/README.md
+3 −0 sw/common/neorv32.ld
+1 −1 sw/example/demo_xip/main.c
+1 −1 sw/lib/include/neorv32_cpu_csr.h
+24 −44 sw/lib/include/neorv32_sysinfo.h
+3 −3 sw/lib/source/neorv32_cpu.c
+57 −43 sw/lib/source/neorv32_rte.c
+14 −16 sw/svd/neorv32.svd
3 changes: 2 additions & 1 deletion radiant/UPduino_v3/README.md
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@@ -1,6 +1,7 @@
# NEORV32 Example Setup for the tinyVision.ai Inc. "UPduino v3.0" FPGA Board

:warning: This setup _requires_ Lattice Radiant version **2022.1**!
> [!WARNING]
> This setup **requires** Lattice Radiant version **2022.1**!
This example setup turns the UPduino v3.0 board, which features a Lattice iCE40 UltraPlus FPGA, into a tiny-scale NEORV32 microcontroller.
The processor setup provides 64kB of data and instruction memory, an RTOS-capable CPU (privileged architecture)
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6 changes: 0 additions & 6 deletions radiant/UPduino_v3/neorv32_upduino_v3.rdf
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Expand Up @@ -69,9 +69,6 @@
<Source name="../../neorv32/rtl/core/neorv32_crc.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_dcache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
Expand All @@ -90,9 +87,6 @@
<Source name="../../neorv32/rtl/core/neorv32_gptmr.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_icache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
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3 changes: 2 additions & 1 deletion radiant/iCEBreaker/README.md
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@@ -1,6 +1,7 @@
# NEORV32 Example Setup for the iCEBreaker FPGA Board

:warning: This setup _requires_ Lattice Radiant version **2022.1**!
> [!WARNING]
> This setup **requires** Lattice Radiant version **2022.1**!
### General

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6 changes: 0 additions & 6 deletions radiant/iCEBreaker/iCEBreaker.rdf
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Expand Up @@ -66,9 +66,6 @@
<Source name="../../neorv32/rtl/core/neorv32_crc.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_dcache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
Expand All @@ -87,9 +84,6 @@
<Source name="../../neorv32/rtl/core/neorv32_gptmr.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_icache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../neorv32/rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
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