remove Zbc tests

they are not part of the RISC-V B ISA extension
stnolting · Apr 4, 2024 · e701dc0 · e701dc0
1 parent 193427e
commit e701dc0
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diff --git a/README.md b/README.md
@@ -12,7 +12,7 @@ This repository is a port of the "**RISCOF** RISC-V Architectural Test Framework
 user and privileged ISA specifications. **Sail RISC-V** is used as reference model.
 Currently, the following tests are supported:
 
-- [x] `rv32i_m\B` - bit-manipulation (`Zba` + `Zbb` + `Zbc` + `Zbs`)
+- [x] `rv32i_m\B` - bit-manipulation (`Zba` + `Zbb` + `Zbs`)
 - [x] `rv32i_m\C` - compressed instructions
 - [x] `rv32i_m\I` - base integer ISA
 - [x] `rv32i_m\M` - hardware integer multiplication and division

diff --git a/plugin-neorv32/neorv32_isa.yaml b/plugin-neorv32/neorv32_isa.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMCUZicsr_Zicond_Zifencei_Zba_Zbb_Zbc_Zbs
+  ISA: RV32IMCUZicsr_Zicond_Zifencei_Zba_Zbb_Zbs
   physical_addr_sz: 32
   User_Spec_Version: "2.3"
   Privilege_Spec_Version: "1.11"

diff --git a/sim/neorv32_riscof_tb.vhd b/sim/neorv32_riscof_tb.vhd
@@ -19,7 +19,7 @@
 -- # ********************************************************************************************* #
 -- # BSD 3-Clause License                                                                          #
 -- #                                                                                               #
--- # Copyright (c) 2023, Stephan Nolting. All rights reserved.                                     #
+-- # Copyright (c) 2024, Stephan Nolting. All rights reserved.                                     #
 -- #                                                                                               #
 -- # Redistribution and use in source and binary forms, with or without modification, are          #
 -- # permitted provided that the following conditions are met:                                     #