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Merge pull request #269 from stnolting/dependabot/submodules/riscv-ar…
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[Dependabot]: Bump riscv-arch-test from `5bc8876` to `ed32d67`
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@stnolting
stnolting committed May 21, 2024
2 parents 5a4dd39 + 0420bcf commit 3a97851
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion riscv-arch-test
Submodule riscv-arch-test updated 43 files
+4 −0 CHANGELOG.md
+1 −1 riscv-test-suite/env/test_macros.h
+1 −1 riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S
+1 −1 riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/froundnx.d_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/D_Zfa/src/froundnx_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S
+1 −1 riscv-test-suite/rv64i_m/F_Zfa/src/froundnx_b1-01.S

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