minor cleanups

README.md

@@ -1,4 +1,4 @@
-# The neoTRNG True Random Number Generator (V3)
+# The neoTRNG True Random Number Generator
 
 **A Tiny and Platform-Independent True Random Number Generator for _any_ FPGA.**
 
@@ -20,16 +20,7 @@
 The neoTRNG aims to be a small and **platform-agnostic** TRUE random number generator (TRNG) that
 can be synthesized for _any_ target technology (FPGAs and even ASICs). It is based on simple free-running
 ring-oscillators, which are enhanced by a _special technique_ in order to allow synthesis for any platform.
-The _phase noise_ that occurs when sampling free-running ring-oscillators is used as physical entropy source. 
-
-**:warning: WARNING** It is possible that there will be at least _some_ cross correlations between external
-signals/events and the generate random numbers. Hence, there is no guarantee at all that the neoTRNG provides
-perfect or cryptographically secure random numbers. Furthermore, there is no tampering detection mechanism or
-online health monitoring available yet to check the integrity of the generated random data.
-
-**:warning: WARNING** Keeping the neoTRNG _permanently enabled_ will increase dynamic power consumption and
-might also cause local heating of the chip (when using very large configurations). Furthermore, additional
-electromagnetic interference (EMI) might be emitted by the design.
+The _phase noise_ that occurs when sampling free-running ring-oscillators is used as physical entropy source.
 
 **Key Features**
 
@@ -39,7 +30,14 @@ electromagnetic interference (EMI) might be emitted by the design.
 * [x] very high operating frequency to ease timing closure
 * [x] easy to use / simple integration
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
+**:warning: WARNING** It is possible that there will be at least _some_ cross correlations between external
+signals/events and the generate random numbers. Hence, there is no guarantee at all that the neoTRNG provides
+perfect or cryptographically secure random numbers. Furthermore, there is no tampering detection mechanism or
+online health monitoring available yet to check the integrity of the generated random data.
+
+**:warning: WARNING** Keeping the neoTRNG _permanently enabled_ will increase dynamic power consumption and
+might also cause local heating of the chip (when using very large configurations). Furthermore, additional
+electromagnetic interference (EMI) might be emitted by the design.
 
 
 ## Top Entity
@@ -86,8 +84,6 @@ first cell. These two generics are further described in the [Architecture](#arch
 The last generic `SIM_MODE` can be set to allow [simulating](#simulation) of the TRNG within a plain RTL
 simulation.
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
-
 
 ## Architecture
 
@@ -107,8 +103,6 @@ bits are sampled / de-serialized by a [shift register](#sampling-unit) to provid
 This shift register also recombines the bits in the stream in order to improve the spectral distribution
 of the random numbers.
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
-
 
 ### Entropy Cells
 
@@ -136,13 +130,11 @@ cell consisting of 5 inverters.
 ![neoTRNG entropy cell - rtl view](https://github.com/raw/stnolting/neoTRNG/main/img/neotrng_cell_rtl.png)
 
 The following image shows the mapping results (generated by Intel Quartus Prime) of the very first entropy
-cell. The latch plus inverter combos of the ring-oscillator chain are mapped to distinct LUT4s that are
+cell. The latch-inverter elements of the ring-oscillator chain are mapped to distinct LUT4s that are
 individually enabled by the shift register FFs.
 
 ![neoTRNG entropy cell - FPGA mapping view](https://github.com/raw/stnolting/neoTRNG/main/img/neotrng_cell_map.png)
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
-
 
 ### De-Biasing
 
@@ -157,8 +149,6 @@ Whenever an edge has been detected a "valid" signal is send to the following sam
 requires at least two clock cycles to generate a single random bit. If no edge is detected (`00` or `11`)
 the valid signal remains low and the sampling unit halts.
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
-
 
 ### Sampling Unit
 
@@ -184,7 +174,7 @@ XORs the input stream with the last bit of the register to further scramble the
         final random byte
 ```
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
+[[back to top](#the-neotrng-true-random-number-generator)]
 
 
 ## Evaluation
@@ -205,8 +195,6 @@ SIM_MODE      = false
 :floppy_disk: A total amount of **4MB** of random data has been obtained for the evaluations. This data set is
 available as `entropy.bin` binary file in the [release](https://github.com/stnolting/neoTRNG/releases) assets.
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
-
 
 ### Histogram Analysis
 
@@ -231,8 +219,6 @@ Max:          16706 = average + 322 at bin 144
 Average dev.: +/- 96
 ```
 
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-
 
 ### Entropy per Byte
 
@@ -294,8 +280,6 @@ neoTRNG:neoTRNG_inst                                      56 (27)            46
 :information_source: Synthesis tools might emit a warning that latches and combinatorial loops
 have been detected. However, this is no design flaw as this is exactly what we want. :wink:
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
-
 
 ### Throughput
 
@@ -305,10 +289,10 @@ The neoTRNG's maximum generation rate is defined by two factors:
 * B = 64: number of raw random bits required by the sampling unit to generate one random byte
 
 Hence, the neoTRNG requires at least `A * B = 2 * 64 = 128` clock cycles to emit one random byte.
-Evaluation have show that the actual sampling time is around ~200 clock cycles. Thus, a system
+Evaluation have show that the actual sampling time is around ~200 clock cycles. Thus, an implementation
 running at 100 MHz can generate up to 500kB of random data per second.
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
+[[back to top](#the-neotrng-true-random-number-generator)]
 
 
 ## Simulation
@@ -360,7 +344,7 @@ The GHDL waveform data is stored to `sim/neoTRNG_tb.ghw` and can be viewed using
 neoTRNG/sim$ gtkwave neoTRNG_tb.ghw
 ```
 
-[[back to top](#the-neotrng-true-random-number-generator-v3)]
+[[back to top](#the-neotrng-true-random-number-generator)]
 
 
 ## References
@@ -369,5 +353,3 @@ neoTRNG/sim$ gtkwave neoTRNG_tb.ghw
 on Hardware-Oriented Security and Trust. IEEE, 2008.
 * Tuncer, Taner, et al. "Implementation of non-periodic sampling true random number generator on FPGA."
 Informacije Midem 44.4 (2014): 296-302.
-
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