leakingZynq

This is a proof of concept about how information can be leaked without any extra HW from an SoC.
The bin file has been synthetized for the Zynq board Pynq from digilent. The pin with the clk routed is the IO5. Any small piece of wire plugged on that pin will improve the emissivity.

FPGA configuration:

$ echo 0 > /sys/class/fpga_manager/fpga0/flags
$ cp leakingZynq_demo_v0.bin /lib/firmware
$ cd /lib/firmware
$ sudo echo leakingZynq_demo_v0.bin > /sys/class/fpga_manager/fpga0/firmware

code compilation and execution

$ cd ~/leakingZynq
$ gcc -Wall -O3 -o pushOut pushOut_v1.c
$ sudo ./pushOut myString

for more info check the file pushOut_v1.c


uart_parse_v4.c is used to demodulate the OOK signal from the arduino+MAX2015 receiver (via uart port)