feat: add course EE202-17 Digital Circuits

courses.md

@@ -11,6 +11,7 @@ class of 2022
 
 ### EE
 - [EE201-17L Analog Circuits Laboratory](courses/EE201-17L.md)
+- [EE202-17 Digital Circuits](courses/EE202-17.md)
 - [EE202-17L Digital Circuits Laboratory](courses/EE202-17L.md)
 - [EE205 Signals and Systems](courses/EE205.md)
 - [EE351 Microprocessors and Microsystems](courses/EE351.md)

courses/EE202-17.md

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+ # EE202-17 Digital Circuits
+
+## Introduction
+Basics of digital circuits, Boolean algebra, combinational and sequential circuits, flip-flops, counters, shift registers, memories, A/D and D/A converters, and digital integrated circuits.
+
+## Notes
+> squarezhong, 2022 Fall, Prof. Yu Yajun
+
+- [Class1-Encode](/courses/ee202-17/Class1-Encode.md)
+- [Class2-CMOS Design](/courses/ee202-17/Class2-CMOS-Design.md)
+- [Class3-Logic Principle](/courses/ee202-17/Class3-Logic-Principle.md)
+- [Class4-Combo Logic](/courses/ee202-17/Class4-Combo-Logic.md)
+- [Class5-Sequential Principle](/courses/ee202-17/Class5-SeqLogic-Principle.md)
+- [Class6-Sequential Logic](/courses/ee202-17/Class6-Sequential-Logic.md)
+- [Class7-Multivibrator&555](/courses/ee202-17/Class7-Multivibrator&555.md)
+- [Class8-Memory](/courses/ee202-17/Class8-Memory.md)
+- [Class9-DAC](/courses/ee202-17/Class9-DAC.md)
+
+## Links

courses/ee202-17/Class1-Encode.md

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+# Digital Circuit
+### Part 1
+
+感悟：电气 (Electrical) 利用电的能量 (Energy), 电子 (Electronic) 利用电的信息 (information)
+
+- 浮点型十进制转化为n进制
+整数部分除n倒排，小数部分乘n正排
+
+- n进制转化为十进制
+加权相加即可
+
+### Part 2
+
+二进制数的表示方式：第一位为符号位（0正1负）
+对于正数 原码=反码=补码
+
+- 正数 -> 负数
+原码(Sign&Magnitude number)：符号位变化
+反码(1s’ complement number)：取反
+补码(2’s complement number)：取反 + 1
+
+补码表示下加减法位数溢出部分直接忽略（只有固定位数是有效值）
+
+- Overflow：只可能在同号相加时发生
+- 注意区分overflow和自然舍弃的区别
+
+![clock_view_of_addition](img/class1/clock_view_of_addition.png)
+
+#### range
+
+- For n-bit binary, the range is:
+
+  | Type           | Range                             |
+  | -------------- | --------------------------------- |
+  | Unsigned       | $0 \to +2^n - 1$                  |
+  | 1’s Complement | $−(2^{n-1} − 1) \to +2^{n-1} − 1$ |
+  | 2’s Complement | $−2^{n-1} \to +2^{n-1} − 1$       |
+
+
+
+
+#### Different codes
+
+1. **BCD (Binary-Coded Decimal) [8421 Code]**
+
+   ![decimal2bcd](img/class1/decimal2bcd.png)
+
+2. **2421 Code 权重为2-4-2-1**
+
+two numbers of 9 complement each other
+
+3. **Excess-3 Code**
+
+表面值 -3 即为实际值
+
+two numbers of 9 complement each other
+
+4. **Gray Code**
+
+the adjacent numbers have only 1 bit different.
+
+![4bit_gray_code](img/class1/4bit_gray_code.png)
+
+5. ASCII Code 
+
+a 7-bit code
+
+
+[Back to Outline](courses/EE202-17.md)

courses/ee202-17/Class2-CMOS-Design.md

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+# Class 2 CMOS-Design
+
+### common logic signs
+
+![common_logic](img/class2/common_logic.png)
+
+![x_or_nor](img/class2/x_or_nor.png)
+
+### Fundamental Elements
+
+- nMOS作驱动器(Pull-down), pMOS作负载器 (Pull-up)
+
+  - PMOS适合传导高电平 (接近VDD), NMOS适合传导低电平(接近GND/VSS).
+
+  - 如果NMOS传输高电平，随着输出电压的上升，Vgs越来越小，一方面电流驱动能力不够，一方面电平损失较大
+
+- 忽略内部实现，关注连接（输出）本质
+- $V_{DD}$和Ground实现了NOT，剩余电路实现了AND/OR
+
+
+
+- AND p并n串
+- OR  p串n并
+
+![nand_gate](img/class2/nand_gate.png)
+
+![nor_gate](img/class2/nor_gate.png)
+
+
+
+#### Noise Margins
+
+mos管是电压控制的原件，不需要额外电流，省电
+
+#### Sink Current (灌电流) and Sourcing Current (拉电流)
+
+#### FANOUT
+
+fanout = min($\displaystyle{\frac{I_{OHmax}}{I_{IHmax}}}$, $\displaystyle{\frac{I_{OLmax}}{I_{ILmax}}}$)
+
+#### Unused Inputs
+
+CMOS inputs不应浮空
+
+
+
+> 以下内容没有在quiz或考试中出现过
+
+#### Rise and Fall times
+
+$t_f \propto R_nC$ where $R_n$ is the “on” resistance of n−transistor. 
+
+$t_r \propto R_pC$ where $R_p$ is the “on” resistance of p−transistor. 
+
+#### Propagation Delay
+
+The time between an input change and the corresponding output change
+
+#### Power Consumption
+
+$P_D = VI = V_{cc}\displaystyle{\frac{dQ}{dt}} = V_{cc}\displaystyle{\frac{C_L dV}{dt}} = C_L \cdot V^2_{CC} \cdot f$
+
+$V_{CC}$: the power supply voltage.
+
+𝑓 : The transition frequency of the output signal. 
+
+$C_L$: Equivalent capacitive load both internally and externally on the output.
+
+[Back to Outline](courses/EE202-17.md)

courses/ee202-17/Class3-Logic-Principle.md

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+# Logic-Principles
+
+- 由truth table得到逻辑表达式
+
+1相加(SOP)，0相乘(POS)
+
+### Boolean Algebra Theorems
+
+![](img/class3/boolean_theorems_1.png)
+
+![](img/class3/boolean_theorems_2.png)
+
+![](img/class3/boolean_theorems_3.png)
+
+
+
+- $X + \bar{X} Y = X + Y$
+
+- Duality 对偶特性
+
+The dual of a logic expression is obtained by swapping 0 and 1, and • and +. (variables do not change)
+
+## K-map
+
+binary sequence of  abc follows <font color='red'>**Gray code**</font>
+
+![](img/class3/kmap_rule.png)
+
+- Each implicant is a **product** term of the function
+
+- implicants (蕴含项)
+
+  - **Prime Implicants**: a group that covers the maximum possible number of adjacent squares.![](img/class3/kmap_prime_implicant.png)
+
+  - **Essential Prime Implicants**: a prime implicant that ==covers a minterm== which is not covered by any other prime implicants![](img/class3/kmap_essential_prime_implicant.png)
+
+### Minimized Logic Fucntions
+
+#### K-map for Sums of Product
+
+**All** essential prime implicants + other **needed** prime implicants
+
+![SOP](img/class3/kmap_SOP.png)
+
+![](img/class3/kmap_4variables.png)
+
+
+
+#### K-map for Product of Sums
+
+![](img/class3/kmap_POS.png)
+
+#### K-map for XOR and XNOR
+
+![2var](img/class3/kmap_xor_xnor_2.png)
+
+![3var](img/class3/kmap_xor_xnor_3.png)
+
+![4var](img/class3/kmap_xor_xnor_4.png)
+
+
+
+#### Odd and Even Functions
+
+- In general, for an n-variable Odd Function, the function is 1 if there are odd number of variables having logic 1
+
+​	e.g. **XOR**
+
+- For an n-variable Even Function, the function is 1 if there are even number of variables having logic 1
+
+​	e.g. **XNOR**
+
+#### DON'T-CARE Conditions
+
+![](img/class3/kmap_not_care.png)
+
+![](img/class3/kmap_not_care_eg.png)
+
+#### 5-variable K-map
+
+![](img/class3/kmap_5variables_1.png)
+
+![](img/class3/kmap_5variables_2.png)
+
+[Back to Outline](courses/EE202-17.md)
+
+
+
+

courses/ee202-17/Class4-Combo-Logic.md

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+# CLASS 4 Combo Logic
+
+### Propagation Delay
+
+Two level delay: if one input is LOW, and the other is changed. 
+
+Three level delay: if one input is HIGH, and the other is changed.
+
+
+
+### Programmable Logic Devices
+
+
+
+- A product term (P) is 1 if no inputs are connected (internal pull up for AND gate).
+-  A product term (P) is 0 if all inputs are connected.
+-  An output term (O) is 0 if no product term is connected
+
+![PLD](./img/class4/PLD.png)
+
+
+
+### Decoder, MUX & Comparator
+
+- Decoder n inputs - 2^n outputs
+
+- (Priority) Encoder 2^n inputs - n outputs
+
+- MUX (e.g.) 2^n inputs - n select signals - 1 output
+
+- DMUX 1 input - n select signals - 2^n output lines
+
+
+
+- for each bit $S_i = A_i B_i + A_i' B_i'$
+
+- Comparator中$I_{A=B}具有最高优先级$
+- Comparator中$I$有效的前提是**Input Number**全部相等
+
+- 默认情况下$I_{A=B}$应置1, 剩余置0
+
+
+
+### Adder
+
+- Subtraction using 2‘s complement
+
+A - B = A + (-B) = A + (B' + 1)
+
+
+
+- Carry-Look-Ahead Adder
+
+$C_{i+1} = G_i + P_iC_i$
+
+Carry Generate $G_i = A_iB_i$
+
+Carry propagate $P_i = A_i\oplus B_i$
+
+$S_i = A_i\oplus B_i\oplus C_i = P_i\oplus C_i$
+
+$C_{i+1} = (A_i B_i + A_i C_i + B_i C_i) = G_i + P_i C_i $
+
+[Back to Outline](courses/EE202-17.md)
+

courses/ee202-17/Class5-SeqLogic-Principle.md

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+# CLASS 5 SeqLogic Principle 
+
+### Latch
+
+$SR\ Latch$ or $\bar{S}\bar{R}\ Latch$
+
+- SR can not be asserted simultaneously
+
+
+
+### Flip-Flop (Clocked Latch)
+
+![next_state_flipflop](img/class5/next_state_flipflop.png)
+
+### State Machine
+
+- Mealy Machine: $output = f(Q, input)$
+- Moore Machine: $output = f(Q)$
+
+#### Equation Definitions
+
+- Characteristic Equation 
+
+  $Q^{\ast} = f(Q, excitation\ signals)$
+
+- Excitation Equation
+
+  $Excitation\ signals = f(Q, input)$
+
+- Transition Equation
+
+  $Q^{\ast} = f(Q, input)$
+
+
+
+- Transition Table -> State Table: xxxx -> S_x
+
+#### State Machine Design (With Flip-Flop)
+
+1. State Diagram
+2. State/Output Table -> Transition/Excitation Table
+3. Excitation Equation
+4. State Machine
+
+[Back to Outline](courses/EE202-17.md)