Lab projects using Verilog HDL in Xilinx ISE
- Adder Multiplier
- Delay Modeling
- GCD
- Natural Number Sum
- Pipelining
- RTC
- Sequence Detector
- Smart Parking
- Memory
- TicTacToe
- Vending Machine
- 4-Stage-Pipeline
- MIPS32
Implementation of multiplier using adiition method.
In this multiplier is designed using the basic idea of adding and shifting the bits,
let say, we have 1 and 2 to multiply which gives output as 2 now we will look how it
works in this algorithm
1 x 2 = 1 + 1 = 2.
Modeling of delays.
This module shows the working of inter and intra delay in a design and how signal behaves with the delays.
Fast gcd algorithm implementation.
This is the implementation of gcd using compare and shift method in which if a > b then a = a - b else b = b-a and if a = b then our gcd is b and if not equal then above are executed until we get a = b hence our gcd comes up in b.
Sum of N Natural Number.
We know to add natural number simply by using loop but in this we are using N(N+1)/2 formula to reduce the use of adder,multiplier and divider and hence reducing cost and time.It is also two stage pipelined in which first stage is fetch which reads data from 1 to 512 from memory and then second stage is execute which makes the sum function.
Three Stage arithmetic operation circuit design pipeling.
This is design of 3-stage pipelined arithmetic unit which calculated addition substraction and multiplication in respective stages,in first stage it calculated x1 = a+b and x2 = c-d and in second stage it calculates y = x1+x2 and last stage gives output z which is z = yxd.
Real Time Clock.
Design of real time clock module which gives outputs in hours:minutes:seconds.
FSM Design of Sequence Detector.
This design detects the sequence 1011 consists of 5 states,first state is idle which when detects 1 then goes to state2 else remains in state1 ,state2 goes to state3 when detects 0 else remains in itself ,state3 goes to state4 when detetcs 1 else goes to state1 and state4 goes to state5 when detetcs 1 else goes to state3 and state5 goes to state1 when input is 1 else in state3.
Smart Parking module IP.
This takes exit and entry sensor data as input when entry sensor detetcs car at door then it asks for password when matches then it opens the door else it asks for password and fills the space when exit sensor detects car then it opens the door and vacant one pace from memory for other cars to fill if required.
Read/Write Memory design.
Simple Read/Wrte(SRAM) memory architecture which gives output data when read signal is high ,when write signal is high it allows user to write data at desired location in memory
TicTacToe game implementation.
This is the design of tictactoe game which allows two players to fit their values into game block(memory) which are x represented by 10 and o represented by 01 and it also gives illegal move signal when player tries to enter their values in place where it is already filled. Winner is decided when someone fills any 3 consecutive blocks first and game gets over when all spaces are filled but no one completes it.
Vending Machine design.
Design of vending machine which has only access to Rs.5,10 and 20 and keeps a count of current total money ,other inputs are refund and return refund of money will be granted when user asks for refund and return allows user to get back their change money. To get soda Rs.55 has to be completed Rs.70 for water ,beep signal is generated when someone tries to get soda/water before completing desired amount.
4-stage pipelined Architecture that carries out following stage-wise operations.
Stage1:Read two 16-bit number from registers specified by rs1 and rs2 and store them in A and B.
Stage2:Perform ALU operations on them specified by func and store in z.
Stage3:Write the value of z in the register specified by rd.
Stage4:Also write the value of z in memory location specified by addr.
5-stage pipelined RISC architecture.
1st stage -> Fetching instruction from Instruction Memory and loading into Instruction Register(IR).
2nd stage -> Decoding instruction and storing into accumulator registers from register bank.
3rd stage -> Executing the instruction based on opcode.
4rth stage -> Loading content of memory if opcode is load or storing ALU outputinto memory if opcodeis store.
5th stage -> Writing back the ALU output into destination registers in register bank.
