Fix AIRCR PRIGROUP mask

[msamsonoff]

Closes #338

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[msamsonoff]

I wonder if it's worth trying to save the PRIGROUP bits at all. They are set to 0b000 during the reset anyway.

[a] aircr: 0xfa050000
[b] aircr: 0xfa050300
sys_reset
[a] aircr: 0xfa050000
[b] aircr: 0xfa050300
sys_reset

That output was generated by this short example program:

#![no_main]
#![no_std]

use cortex_m::asm;
use cortex_m_rt::entry;
use cortex_m_semihosting::hprintln;
use panic_semihosting as _;
use stm32h7 as _;

const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x7 << 8;
const SCB_AIRCR_PRIGROUP: u32 = 0x03 << 8;

#[entry]
fn main() -> ! {
    let p = cortex_m::Peripherals::take().unwrap();
    let scb = p.SCB;

    hprintln!("[a] aircr: 0x{:08x}", scb.aircr.read()).unwrap();

    asm::dsb();
    unsafe {
        scb.aircr.modify(
            |r| {
                SCB_AIRCR_VECTKEY | (r & SCB_AIRCR_PRIGROUP_MASK) | SCB_AIRCR_PRIGROUP
            }
        )
    }
    asm::dsb();

    hprintln!("[b] aircr: 0x{:08x}", scb.aircr.read()).unwrap();
    hprintln!("sys_reset").unwrap();

    cortex_m::peripheral::SCB::sys_reset();
}

[thejpster]

I guess someone might change them? Anyway, 0x05 looks wrong and 0x07 looks right, so I'm happy with this after looking at section B3.2.6 of the Arm Armv7-M ARM.

[thejpster]

bors r+

[bors]

👎 Rejected by too few approved reviews

[thejpster]

bors retry

[bors]

Build succeeded:

• ci-linux (1.38.0)
• ci-linux (stable)
• clippy
• rustfmt