[RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration #1632
Conversation
| struct { | ||
| uint8_t reg:7; | ||
| uint8_t single:1; | ||
| uint8_t reg:5; |
There was a problem hiding this comment.
If there is only 16 regs then we have a problem, and cannot use fixed register position as for arm64, because that would leave 0 scratch register!
We need sommething more dynamic, like YMM handling on ARM64, because we need more than 16regs!
There was a problem hiding this comment.
wait... it stores the native register number, not the sse register number, then there is 32 of them, and we need a uint16_t.
There was a problem hiding this comment.
I reverted the change, sorry.
There was a problem hiding this comment.
reverted partly... 5bits should be enough yes.
There was a problem hiding this comment.
5 bits are not enough I think, because we use -1 to indicate the register is forgotten, so there needs at least 1 bit free to not conflict with -1.
There was a problem hiding this comment.
then have a "isfree:1", it will be set to "1" when .v=-1
There was a problem hiding this comment.
sorry not sure I followed, but what you suggested on "revert partly" is this?
uint16_t reg:5;
uint16_t vector:1;
uint16_t single:1;
uint16_t write:1;
uint16_t isfree:1;
uint16_t unused:7;
There was a problem hiding this comment.
Yes. And this isfree need to be set to 0 when used...
|
@ptitSeb please do another round of review, thanks. |
…tration (ptitSeb#1632) * [RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration * keep sse_cache_s uint8_t as suggested * use xor to do the wrap * revert * better fallback
No description provided.