The verilog codes are writen with gedit on Ubuntu using the following commands in terminal:
gedit module.v1. For separate module and testbench files
iverilog -o testbench_tb.vvp testbench_tb.v2. For a single file
iverilog -Wall module.v unbuffer vvp a.out.vvp can be generated in Ubuntu using the following command:
vvp testbench_tb.vvp
gtkwave dumpfile.vcdAlternatively, GTKWave can be opened by simply clicking on the dumpfile.vcd file created in your workspace folder after the previous command.