Popular repositories Loading

1. open-register-design-tool open-register-design-tool Public

   Forked from Juniper/open-register-design-tool

   Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

   Verilog

2. neorv32 neorv32 Public

   Forked from stnolting/neorv32

   🖥️ A size-optimized, customizable MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

   VHDL

3. XKCP XKCP Public

   Forked from XKCP/XKCP

   eXtended Keccak Code Package

   C