feat: add support for STM32G474VxT (#372)

* feat: add support for STM32G474VxT note: no QUADSPI and FMC support, yet * Apply suggestions from code review Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --------- Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
philips-software · Aug 7, 2024 · fe9ee42 · fe9ee42
1 parent edbd1e3
commit fe9ee42
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Showing 6 changed files with 1,318 additions and 10 deletions.
diff --git a/CMakePresets.json b/CMakePresets.json
@@ -145,7 +145,8 @@
       "cacheVariables": {
         "TARGET_CORTEX": "m4",
         "TARGET_MCU_FAMILY": "stm32g4xx",
-        "TARGET_MCU": "stm32g474"
+        "TARGET_MCU": "stm32g474",
+        "TARGET_MCU_VARIANT": "stm32g474rxt"
       }
     },
     {

diff --git a/hal_st/stm32fxxx/CMakeLists.txt b/hal_st/stm32fxxx/CMakeLists.txt
@@ -35,8 +35,8 @@ target_sources(hal_st.stm32fxxx PRIVATE
     $<$<STREQUAL:${TARGET_MCU},stm32g070>:DefaultClockNucleoG070RB.hpp>
     $<$<STREQUAL:${TARGET_MCU},stm32g431>:DefaultClockNucleoG431RB.cpp>
     $<$<STREQUAL:${TARGET_MCU},stm32g431>:DefaultClockNucleoG431RB.hpp>
-    $<$<STREQUAL:${TARGET_MCU},stm32g474>:DefaultClockNucleoG474RE.cpp>
-    $<$<STREQUAL:${TARGET_MCU},stm32g474>:DefaultClockNucleoG474RE.hpp>
+    $<$<STREQUAL:${TARGET_MCU},stm32g474>:DefaultClockNucleoG474xxx.cpp>
+    $<$<STREQUAL:${TARGET_MCU},stm32g474>:DefaultClockNucleoG474xxx.hpp>
     $<$<STREQUAL:${TARGET_MCU},stm32wb55>:DefaultClockNucleoWB55RG.cpp>
     $<$<STREQUAL:${TARGET_MCU},stm32wb55>:DefaultClockNucleoWB55RG.hpp>
     $<$<STREQUAL:${TARGET_MCU},stm32wba52>:DefaultClockNucleoWBA52CG.cpp>
@@ -119,9 +119,16 @@ if (TARGET_MCU_VENDOR STREQUAL st)
     elseif (TARGET_MCU STREQUAL stm32g431)
         set(gpio_xml "${CMAKE_CURRENT_SOURCE_DIR}/ip/GPIO-STM32G43x_gpio_v1_0_Modes.xml")
         set(mcu_xml "${CMAKE_CURRENT_SOURCE_DIR}/mcu/STM32G431R(6-8-B)Tx.xml")
-    elseif (TARGET_MCU STREQUAL stm32g474)
-        set(gpio_xml "${CMAKE_CURRENT_SOURCE_DIR}/ip/GPIO-STM32G47x_gpio_v1_0_Modes.xml")
-        set(mcu_xml "${CMAKE_CURRENT_SOURCE_DIR}/mcu/STM32G474R(B-C-E)Tx.xml")
+    elseif(TARGET_MCU STREQUAL stm32g474)
+        if (TARGET_MCU_VARIANT STREQUAL stm32g474rxt)
+            set(gpio_xml "${CMAKE_CURRENT_SOURCE_DIR}/ip/GPIO-STM32G47x_gpio_v1_0_Modes.xml")
+            set(mcu_xml "${CMAKE_CURRENT_SOURCE_DIR}/mcu/STM32G474R(B-C-E)Tx.xml")
+        elseif (TARGET_MCU_VARIANT STREQUAL stm32g474vxt)
+            set(gpio_xml "${CMAKE_CURRENT_SOURCE_DIR}/ip/GPIO-STM32G47x_gpio_v1_0_Modes.xml")
+            set(mcu_xml "${CMAKE_CURRENT_SOURCE_DIR}/mcu/STM32G474V(B-C-E)Tx.xml")
+        else()
+            message(FATAL_ERROR "Unknown TARGET_MCU_VARIANT \"${TARGET_MCU_VARIANT}\". Please configure HALST_XML_GPIO and HALST_XML_STM32.")
+        endif()
     elseif (TARGET_MCU_VARIANT STREQUAL stm32wb55rg)
         set(gpio_xml "${CMAKE_CURRENT_SOURCE_DIR}/ip/GPIO-STM32WB55x_gpio_v1_0_Modes.xml")
         set(mcu_xml "${CMAKE_CURRENT_SOURCE_DIR}/mcu/STM32WB55RGVx.xml")
@@ -143,6 +150,9 @@ if (TARGET_MCU_VENDOR STREQUAL st)
     elseif (TARGET_MCU_FAMILY STREQUAL stm32wbaxx)
         generate_xslt(hal_st.stm32fxxx generated/stm32fxxx/PeripheralTableStructure.xml GeneratePeripheralTableStructure.xsl PeripheralTableWbaxx.xml
         --stringparam mcu-document ${mcu_xml})
+    elseif (TARGET_MCU_FAMILY STREQUAL stm32g4xx)
+        generate_xslt(hal_st.stm32fxxx generated/stm32fxxx/PeripheralTableStructure.xml GeneratePeripheralTableStructure.xsl PeripheralTableGxxx.xml
+        --stringparam mcu-document ${mcu_xml})
     else()
         generate_xslt(hal_st.stm32fxxx generated/stm32fxxx/PeripheralTableStructure.xml GeneratePeripheralTableStructure.xsl PeripheralTableFxxx.xml
         --stringparam mcu-document ${mcu_xml})

diff --git a/...st/stm32fxxx/DefaultClockNucleoG474RE.cpp → ...t/stm32fxxx/DefaultClockNucleoG474xxx.cpp b/...st/stm32fxxx/DefaultClockNucleoG474RE.cpp → ...t/stm32fxxx/DefaultClockNucleoG474xxx.cpp
@@ -1,5 +1,5 @@
 #include DEVICE_HEADER
-#include "hal_st/stm32fxxx/DefaultClockNucleoG474RE.hpp"
+#include "hal_st/stm32fxxx/DefaultClockNucleoG474xxx.hpp"
 
 /* The system Clock is configured as follows:
  *    System Clock source            = PLL (HSE)
@@ -8,11 +8,12 @@
  *    AHB Prescaler                  = 1
  *    APB1 Prescaler                 = 1
  *    APB2 Prescaler                 = 1
- *    HSI Frequency(Hz)              = 24MHz
+ *    HSE Frequency(Hz)              = 24MHz
+ *    HSI Frequency(Hz)              = 16MHz
  *    VDD(V)                         = 3.3
  *    Main regulator output voltage  = Scale1 mode
  */
-void ConfigureDefaultClockNucleo474RE()
+void ConfigureDefaultClockNucleoG474xxx()
 {
     RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
     RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };

diff --git a/...st/stm32fxxx/DefaultClockNucleoG474RE.hpp → ...t/stm32fxxx/DefaultClockNucleoG474xxx.hpp b/...st/stm32fxxx/DefaultClockNucleoG474RE.hpp → ...t/stm32fxxx/DefaultClockNucleoG474xxx.hpp
@@ -1,6 +1,6 @@
 #ifndef HAL_ST_DEFAULT_CLOCK_HPP
 #define HAL_ST_DEFAULT_CLOCK_HPP
 
-void ConfigureDefaultClockNucleo474RE();
+void ConfigureDefaultClockNucleoG474xxx();
 
 #endif
diff --git a/hal_st/stm32fxxx/PeripheralTableGxxx.xml b/hal_st/stm32fxxx/PeripheralTableGxxx.xml
@@ -0,0 +1,61 @@
+<?xml version="1.0"?>
+<peripherals xmlns:xi="http://www.w3.org/2001/XInclude">
+  <peripheral name="Uart" type="USART_TypeDef*">
+    <item name="UART"/>
+    <item name="USART"/>
+    <interrupt/>
+  </peripheral>
+  <peripheral name="Spi" type="SPI_TypeDef*"><item name="SPI"/><interrupt/></peripheral>
+  <peripheral name="I2c" type="I2C_TypeDef*"><item name="I2C"/>
+    <interrupt name="Ev" postfix="_EV"/>
+    <interrupt name="Er" postfix="_ER"/>
+  </peripheral>
+  <peripheral name="Sai" type="SAI_TypeDef*"><item name="SAI"/>
+    <interrupt/>
+  </peripheral>
+  <peripheral name="Sd" type="SD_TypeDef*"><item name="SDMMC"/>
+    <interrupt/>
+  </peripheral>
+  <!--
+  Disabled, the G474VeT doesn't have an SDRAM capable FMC. Only SRAM/PSRAM (and more)
+
+  <peripheral name="SdRam" type="FMC_SDRAM_TypeDef" base="FMC_R_BASE">
+    <item name="FMC"/>
+  </peripheral>
+  -->
+  <peripheral name="Can" type="CAN_TypeDef*"><item name="CAN"/>
+    <interrupt name="Tx" postfix="_TX"/>
+    <interrupt name="Rx0" postfix="_RX0"/>
+    <interrupt name="Rx1" postfix="_RX1"/>
+    <interrupt name="Sce" postfix="_SCE"/>
+  </peripheral>
+  <peripheral name="Timer" type="TIM_TypeDef*" prefix="TIM">
+    <item name="TIM1_8"/>
+    <item name="TIM6_7"/>
+    <item name="TIM1_8F7"/>
+    <item name="TIM6_7F7"/>
+    <item name="TIM1_8F37"/>
+    <item name="TIM6_7F37"/>
+    <item name="TIM1_8F77"/>
+    <item name="TIM6_7F77"/>
+  </peripheral>
+  <peripheral name="Adc" type="ADC_TypeDef*"><item name="ADC"/></peripheral>
+  <peripheral name="Dac" type="DAC_TypeDef*"><item name="DAC"/></peripheral>
+  <peripheral name="Ethernet" type="ETH_TypeDef*">
+    <item name="ETH"/>
+    <interrupt/>
+  </peripheral>
+  <peripheral name="USB" type="USB_OTG_GlobalTypeDef*" base="USB_OTG_HS_PERIPH_BASE">
+    <item name="USB_OTG_FS"/>
+  </peripheral>
+  <!--
+  Disabled, IRQn generated as QUADSPI1_IRQn, but the G474VxT uses QUADSPI_IRQn
+
+  <peripheral name="QuadSpi" type="QUADSPI_TypeDef*" base="QSPI_R_BASE">
+    <item name="QUADSPI"/>
+    <interrupt/>
+  </peripheral>
+  -->
+  <peripheral name="Rng" type="RNG_TypeDef*"><item name="RNG"/></peripheral>
+  <peripheral name="Rtc" type="RTC_TypeDef*"><item name="RTC"/></peripheral>
+</peripherals>