This is a collection of simple RISC V (rv32i) cores for teaching purposes. They are written in a subset of SystemVerilog understood by Yosys, the open-source hardware synthesis framework, and Verilator, an open-source Verilog to C++ compiler. The implementation is extremely simple, no bells and whistles, and it's modularized sensibly, so that schematics generated by synthesis tools are readable.
Three cores are currently implemented:
- single-cycle core (one instruction per cycle, separate instruction and data bus),
- multicycle core (multiple cycles per instruction, single memory bus, only one adder),
- pipelined core (five-stage pipeline).
The single-cycle core is adapted from riscv-simple. Code structure has been modified for readability, and several bugs have been fixed.
The cores are tested using official unit tests.