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- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
riscv-isa-manual
Publicriscv-fast-interrupt
Publicriscv-j-extension
Publicriscv-opcodes
Publicriscv-zalasr
Publicdocs-resources
Publicdocs-dev-guide
Publicriscv-performance-events
Publicself-hosted-trace
Publicft-trigger-delegation
Publicmeta-riscv
PublicOpenEmbedded/Yocto layer for RISC-V Architectureriscv-zilsd
Publicriscv-debug-spec
Publicconfiguration-structure
Publicriscv-spmp
PublicThe repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.riscv-glossary
Publicriscv-aia
Publicriscv-double-trap
Publicdocs-spec-template
Public template- This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
riscv-dot-product
Publicriscv-bfloat16
Publicriscv-cfi
PublicThis repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.