You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
I noticed these two differential signals were swapped in the r0.2 schematic. I've never done a DDR design and was wondering if there was a reason for this or if it snuck in during layout?
The text was updated successfully, but these errors were encountered:
DQSs are connected properly (although signal name is wrong), but DMs are not. As a result, when bytes are written one at a time and read back in group of 4 bytes, they are swapped. We discovered this in this function, with debug lines added - recv is the data from PRINT_GETC() and signature is what the function returns:
I noticed these two differential signals were swapped in the r0.2 schematic. I've never done a DDR design and was wondering if there was a reason for this or if it snuck in during layout?
The text was updated successfully, but these errors were encountered: