Home

Welcome to the mor1kx wiki!

Table of Contents Introduction Get started Get in touch Implementation statistics Code Size Licensing

Introduction

The mor1kx is an OpenRISC 1000 (or1k) compliant CPU implementation which is written in synthesisable Verilog.

There's more documentation in AsciiDoc format in the doc/ path.

The mor1kx is a verilog core providing many parameters to allow customising to your exact needs. Please refer to the parameter documentation for details

Get started

See this guide on setting up and using a simulation environment for the mor1kx core.

Get in touch

Email the OpenRISC mailing lists.

Chat with us in #openrisc on irc.freenode.net.

Implementation statistics

This is on a page of its own.

Code Size

Using "cloc --force-lang="C" *.v" we have the following statistics for mor1kx at the v2.1 release:

-------------------------------------------------------------------------------
Language                     files          blank        comment           code
-------------------------------------------------------------------------------
C                               39           2340           2981          12228
-------------------------------------------------------------------------------

Licensing

This work is intended to be open source, but because there are no obviously appropriate licenses to achieve copy left for hardware designs (ultimately what RTL code becomes in ASICs - it's less obvious what it becomes in FPGAs) it's licensed under the Open Hardware Description License which I (Julius) made up out of the Mozilla Public License 2.0.

I want a weak copy-left hardware so ASIC designers can collaborate with us without fear of having to divulge the proprietary portions of the chip, which a strong copy-left license would require. Getting something back is better than getting nothing back.

If you don't like it, my license lets you relicense this work under the GPLs (are you crazy?!) or the more considered CERN OHL.

Licensing rant over.