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[BUG] Ariane incorrectly treats NaNs as zeros for simple precision floating-point arithmetics #1071

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flaviens opened this issue Feb 16, 2023 · 7 comments
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter Status:New Newly created issue, nobody has looked at it yet. Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@flaviens
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flaviens commented Feb 16, 2023

I discovered that Ariane unexpectedly sets the NV (invalid operation) when we call fdiv.s on floating-point operands that have the 32 lower bits as zeros but are NaNs.

Example snippet to reproduce:

  .section ".text.init","ax",@progbits
  .globl _start
  .align 2
_start:

  # Enable the FPU
  li t0, 0x2000
  csrs mstatus, t0
  csrw	fcsr,x0

  la t0, .fdata0
  la t1, .fdata1
  fld ft0, (t0)
  fld ft1, (t1)

  fdiv.s ft2, ft0, ft1
  csrr t2, fflags

infinite_loop:
  j infinite_loop

.section ".fdata0","ax",@progbits
  .8byte 0x49a3e80e00000000
.section ".fdata1","ax",@progbits
  .8byte 0xa81ad47700000000

From spike, fflags should be clear, but Ariane sets fflags=0x10, which corresponds to NV.
Let me know if I can help debug that.

Note: this may be an issue proper to the FPU, not yet entirely sure.

Thanks!
Flavien

@flaviens flaviens added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Feb 16, 2023
@flaviens flaviens changed the title [BUG] Ariane incorrectly treats NaNs as zeros for simple precision arithmetics [BUG] Ariane incorrectly treats NaNs as zeros for simple precision floating-point arithmetics Feb 16, 2023
@MikeOpenHWGroup MikeOpenHWGroup added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Status:New Newly created issue, nobody has looked at it yet. labels Feb 16, 2023
@MikeOpenHWGroup
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Hi @flaviens, this is a known issue with a complex history. As you may know, the CVA6 is using a version of the PULP Platform FPNEW floating point unit. This IP has been transfered to OpenHW and rebranded as CVFPU. This IP is undergoing several updates and full verification as part of the CV32E40P v2 project.

The CVA6 will integrate CVFPU once it has been fully verified in the E40P project. However, there is currently no timeline for this as the current CVA6 device under development (CV32A6) does not support the F and D ISAs.

@flaviens
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Hi @MikeOpenHWGroup, thank you for your prompt reply! You say it is a known issue but I could not find a mention of it anywhere. Can you please show where it is documented?
Thanks!

@JeanRochCoulon
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Hello @flaviens CVA6 FPU has just been updated ! I hope this has solved the issue. Can I ask you to verify it and close the issue if it is ok on your side ?

@flaviens
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Hi @JeanRochCoulon thanks for the notification! What improvements do you expect: just this issue or all pending FPU issues to be fixed?

@JeanRochCoulon
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Hello @flaviens,
Concerning the current issue, if it is fixed, do not hesitate to close.
Of course, it would be better to challenge all the FPU functionalities. So, if you find other bugs, I would encourage you to enter new github issues. Thanks for your feedback.

@flaviens
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Thank you for your response!
Does the FPU update intend to fix all the yet reported FPU issues in fpnew (e.g., but not limited to this one)?
Thanks!

@flaviens
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I close this one but this issue shares similarities

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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter Status:New Newly created issue, nobody has looked at it yet. Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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