Gateware issues

[jonnew]

Testing of these devices seems to be revealing intermittent issues in the gateware:

1. One channel in 384 of both the LFP and Spike streams always seems to produce 0 values. This value appears in the first frame of a superframe, but its position changes between resets. Aside from the obviously incorrect value, the location switch leads to a lack of confidence in a consistent channel mapping between runs
2. The hub clock is placed at the end of the frame which is at least non-conventional
3. The sync words are included in the data frame, but are not used
4. The amplifier data is non-contiguous and should be reordered in the gateware to remove counter and reserved segments
5. The Q11.5 -> Q11 conversion should be done on the FPGA instead of packing fixed point values into the frame for no reason (10 bit ADC determines sample resolution, the extra 5 bits are useless)