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RTL_DIR = $(PWD) | ||
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.PHONY:lint | ||
lint: | ||
@verilator --lint-only $(RTL_DIR)/*.sv | ||
@verible-verilog-lint $(RTL_DIR)/*.sv |
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`default_nettype none | ||
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module recirculation_mux | ||
# | ||
( | ||
parameter int G_STAGES = 2, | ||
parameter int G_WIDTH = 4 | ||
) | ||
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( | ||
input logic i_clk_A, | ||
input logic i_rst_A, | ||
input logic i_pulse_A, | ||
input logic [G_WIDTH - 1 : 0] i_data_A, | ||
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input logic i_clk_B, | ||
input logic i_rst_B, | ||
output logic [G_WIDTH - 1 : 0] o_data_B | ||
); | ||
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logic w_pulse_B; | ||
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toggle_synchronizer #(.G_STAGES(G_STAGES)) sync (.*,.o_pulse_B(w_pulse_B)); | ||
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always_ff @(posedge i_clk_B) begin : mux_recirculation | ||
if(i_rst_B) begin | ||
o_data_B <= 0; | ||
end else begin | ||
if (w_pulse_B) | ||
o_data_B <= i_data_A; | ||
end | ||
end | ||
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endmodule : recirculation_mux |
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`default_nettype none | ||
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module toggle_synchronizer | ||
# | ||
( | ||
parameter int G_STAGES = 2 | ||
) | ||
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( | ||
input logic i_clk_A, | ||
input logic i_rst_A, | ||
input logic i_pulse_A, | ||
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input logic i_clk_B, | ||
input logic i_rst_B, | ||
output logic o_pulse_B | ||
); | ||
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logic r_pulse_A; | ||
logic [G_STAGES - 1 : 0] r_syncB_pulse_A; | ||
logic r_edge_detect_ff; | ||
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always_ff @(posedge i_clk_A) begin : pulse_to_level | ||
if(i_rst_A) begin | ||
r_pulse_A <= 0; | ||
end else begin | ||
if (i_pulse_A) | ||
r_pulse_A <= ~r_pulse_A; | ||
end | ||
end | ||
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always_ff @(posedge i_clk_B) begin : sync_domain_B | ||
if(i_rst_B) begin | ||
r_syncB_pulse_A <= '0; | ||
r_edge_detect_ff <= 1'b0; | ||
end else begin | ||
r_syncB_pulse_A <= {r_syncB_pulse_A[G_STAGES - 2 : 0], r_pulse_A}; | ||
r_edge_detect_ff <= r_syncB_pulse_A[G_STAGES - 1]; | ||
end | ||
end | ||
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assign o_pulse_B = r_edge_detect_ff ^ r_syncB_pulse_A[G_STAGES - 1]; | ||
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endmodule : toggle_synchronizer |