restructured repo in anticipation of adding a SV implementation

npatsiatzis · Aug 17, 2023 · 3cf2ccd · 3cf2ccd
1 parent 299be2c
commit 3cf2ccd
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Showing 6 changed files with 9 additions and 9 deletions.
diff --git a/cocotb_sim/Makefile b/cocotb_sim/Makefile
@@ -6,8 +6,8 @@ TOPLEVEL_LANG ?= vhdl
 EXTRA_ARGS += --std=08
 SIM_ARGS += --wave=wave.ghw
 
-VHDL_SOURCES += $(PWD)/../rtl/toggle_synchronizer.vhd
-VHDL_SOURCES += $(PWD)/../rtl/recirculation_mux.vhd
+VHDL_SOURCES += $(PWD)/../rtl/VHDL/toggle_synchronizer.vhd
+VHDL_SOURCES += $(PWD)/../rtl/VHDL/recirculation_mux.vhd
 # use VHDL_SOURCES for VHDL files
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file

diff --git a/cocotb_sim/test_recirculation_mux.py b/cocotb_sim/test_recirculation_mux.py
@@ -18,8 +18,8 @@ def test_recirculation_mux(parameter):
     module = "testbench"
     toplevel = "recirculation_mux"   
     vhdl_sources = [
-        os.path.join(rtl_dir, "../rtl/toggle_synchronizer.vhd"),
-        os.path.join(rtl_dir, "../rtl/recirculation_mux.vhd"),
+        os.path.join(rtl_dir, "../rtl/VHDL/toggle_synchronizer.vhd"),
+        os.path.join(rtl_dir, "../rtl/VHDL/recirculation_mux.vhd"),
         ]
 
 
@@ -47,7 +47,7 @@ def test_toggle_synchronize(parameter):
     module = "testbench_toggle"
     toplevel = "toggle_synchronizer"   
     vhdl_sources = [
-        os.path.join(rtl_dir, "../rtl/toggle_synchronizer.vhd"),
+        os.path.join(rtl_dir, "../rtl/VHDL/toggle_synchronizer.vhd"),
         ]
 
 

diff --git a/pyuvm_sim/Makefile b/pyuvm_sim/Makefile
@@ -6,8 +6,8 @@ TOPLEVEL_LANG ?= vhdl
 EXTRA_ARGS += --std=08
 SIM_ARGS += --wave=wave.ghw
 
-VHDL_SOURCES += $(PWD)/../rtl/toggle_synchronizer.vhd
-VHDL_SOURCES += $(PWD)/../rtl/recirculation_mux.vhd
+VHDL_SOURCES += $(PWD)/../rtl/VHDL/toggle_synchronizer.vhd
+VHDL_SOURCES += $(PWD)/../rtl/VHDL/recirculation_mux.vhd
 # use VHDL_SOURCES for VHDL files
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file

diff --git a/pyuvm_sim/test_pyuvm_recirculation_mux.py b/pyuvm_sim/test_pyuvm_recirculation_mux.py
@@ -18,8 +18,8 @@ def test_recirculation_mux(parameter):
     module = "tb"
     toplevel = "recirculation_mux"   
     vhdl_sources = [
-        os.path.join(rtl_dir, "../rtl/toggle_synchronizer.vhd"),
-        os.path.join(rtl_dir, "../rtl/recirculation_mux.vhd"),
+        os.path.join(rtl_dir, "../rtl/VHDL/toggle_synchronizer.vhd"),
+        os.path.join(rtl_dir, "../rtl/VHDL/recirculation_mux.vhd"),
         ]
 
 

diff --git a/rtl/recirculation_mux.vhd → rtl/VHDL/recirculation_mux.vhd b/rtl/recirculation_mux.vhd → rtl/VHDL/recirculation_mux.vhd
diff --git a/rtl/toggle_synchronizer.vhd → rtl/VHDL/toggle_synchronizer.vhd b/rtl/toggle_synchronizer.vhd → rtl/VHDL/toggle_synchronizer.vhd