updated README files

README.md

@@ -20,3 +20,4 @@
 - [cocotb](https://github.com/npatsiatzis/fifo_asynchronous/tree/main/cocotb_sim)
 - [pyuvm](https://github.com/npatsiatzis/fifo_asynchronous/tree/main/pyuvm_sim)
 - [uvm](https://github.com/npatsiatzis/fifo_asynchronous/tree/main/uvm_sim)
+- [verilator](https://github.com/npatsiatzis/fifo_asynchronous/tree/main/verilator_sim)

verilator_sim/README.MD

@@ -0,0 +1,18 @@
+### asynchronous FIFO RTL implementation
+
+
+- used to communicate data between 2 asynchronous clock domains
+- Gray fifo pointers for avoiding data incoherency
+- configurable FIFO depth and width
+- logic for generating empty/full
+
+-- Verilator tb for functional verification, adapted from the work of Norbet Kremeris (https://www.itsembedded.com/dhd/verilator_4/). Added coverage class for the input and output interfaces,sequence class, coverage-based end-of-test condition and coverage-driven test generation
+-- Verilator support for multiple clock domains adopted from https://josuah.net/blog/2022-05-18/.
+
+- run sim
+    - $ make sim
+- Achieve full point coverage for output
+- open waveform with gtkwave
+    - $ make waves
+- lint test
+    - $make lint