3x1-Router-Verilog-

Yash Motagi uni: Esigelec(Rouen) France, email:motagiyash@gmail.com

3x1 Router RTL Design in Verilog.

The overall design is working perfectly. individual files are working perfectly.

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
README.md		README.md
fifo.v		fifo.v
fsm.v		fsm.v
reg.v		reg.v
sync.v		sync.v
top.v		top.v

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