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Merge pull request #3 from esl-epfl/merge_cv32e40p
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merge cv32e40p
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@davideschiavone
davideschiavone committed Jan 17, 2024
2 parents b079236 + 12ee46f commit 49770e7
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Showing 22 changed files with 580 additions and 329 deletions.
12 changes: 6 additions & 6 deletions bhv/cv32e40px_instr_trace.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -679,22 +679,22 @@ class instr_trace_t;
// decode and print instruction
case (instr[11:8])
// cv.starti, cv.endi
4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, rd[0], imm_iz_type);
4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, instr[7], imm_iz_type);
// cv.counti
4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, rd[0], imm_iz_type);
4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, instr[7], imm_iz_type);
// cv.start, cv.end, cv.count
4'b0001, 4'b0011, 4'b0101: begin
regs_read.push_back('{rs1, rs1_value, 0});
str = $sformatf("%-16s %d, %s", mnemonic, rd[0], regAddrToStr(rs1));
str = $sformatf("%-16s %d, %s", mnemonic, instr[7], regAddrToStr(rs1));
end
// cv.setupi
4'b0110: begin
str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, rd[0], imm_iz_type, rs1);
str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, instr[7], imm_iz_type, rs1);
end
// cv.setup
4'b0111: begin
regs_read.push_back('{rs1, rs1_value, 0});
str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, rd[0], regAddrToStr(rs1), imm_iz_type);
str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, instr[7], regAddrToStr(rs1), imm_iz_type);
end
endcase
end
Expand Down Expand Up @@ -861,7 +861,7 @@ class instr_trace_t;
endcase
str_sci = "";
end

// shuffle/pack
6'b110000: begin
if (instr[14:12] == 3'b111) begin
Expand Down
275 changes: 169 additions & 106 deletions bhv/cv32e40px_rvfi.sv
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30 changes: 24 additions & 6 deletions bhv/cv32e40px_tb_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -272,13 +272,19 @@ module cv32e40px_tb_wrapper

.rs1_addr_id_i (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_ra_id),
.rs2_addr_id_i (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_rb_id),
.rs3_addr_id_i (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_rc_id),
.operand_a_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_a_fw_id),
.operand_b_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_b_fw_id),
.operand_c_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_c_fw_id),
// .instr (cv32e40px_top_i.core_i.id_stage_i.instr ),
.is_compressed_id_i(cv32e40px_top_i.core_i.id_stage_i.is_compressed_i),
.ebrk_insn_dec_i (cv32e40px_top_i.core_i.id_stage_i.ebrk_insn_dec),
.csr_cause_i (cv32e40px_top_i.core_i.csr_cause),
.debug_csr_save_i (cv32e40px_top_i.core_i.debug_csr_save),
.ecall_insn_dec_i (cv32e40px_top_i.core_i.id_stage_i.ecall_insn_dec),
.mret_insn_dec_i (cv32e40px_top_i.core_i.id_stage_i.mret_insn_dec),
.mret_dec_i (cv32e40px_top_i.core_i.id_stage_i.mret_dec),

.csr_cause_i (cv32e40px_top_i.core_i.csr_cause),
.debug_csr_save_i(cv32e40px_top_i.core_i.debug_csr_save),

// HWLOOP regs
.hwlp_start_q_i (hwlp_start_q),
Expand All @@ -298,14 +304,16 @@ module cv32e40px_tb_wrapper
.apu_multicycle_i (cv32e40px_top_i.core_i.ex_stage_i.apu_multicycle),
.wb_contention_lsu_i(cv32e40px_top_i.core_i.ex_stage_i.wb_contention_lsu),
.wb_contention_i (cv32e40px_top_i.core_i.ex_stage_i.wb_contention),

.regfile_we_lsu_i (cv32e40px_top_i.core_i.ex_stage_i.regfile_we_lsu),
// .rf_we_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_we_fw_i),
// .rf_addr_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i),
// .rf_wdata_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i),

.mult_ready_i (cv32e40px_top_i.core_i.ex_stage_i.mult_ready),
.alu_ready_i (cv32e40px_top_i.core_i.ex_stage_i.alu_ready),
//// WB probes ////
.wb_valid_i(cv32e40px_top_i.core_i.wb_valid),

.wb_valid_i (cv32e40px_top_i.core_i.wb_valid),
.wb_ready_i (cv32e40px_top_i.core_i.lsu_ready_wb),
//// LSU probes ////
.data_we_ex_i (cv32e40px_top_i.core_i.data_we_ex),
.data_atop_ex_i (cv32e40px_top_i.core_i.data_atop_ex),
Expand All @@ -325,6 +333,8 @@ module cv32e40px_tb_wrapper
.lsu_ready_ex_i (cv32e40px_top_i.core_i.lsu_ready_ex),
.lsu_ready_wb_i (cv32e40px_top_i.core_i.lsu_ready_wb),

.lsu_data_be_i(cv32e40px_top_i.core_i.load_store_unit_i.data_be),

.data_req_pmp_i(cv32e40px_top_i.core_i.data_req_pmp),
.data_gnt_pmp_i(cv32e40px_top_i.core_i.data_gnt_pmp),
.data_rvalid_i(cv32e40px_top_i.core_i.data_rvalid_i),
Expand All @@ -339,11 +349,12 @@ module cv32e40px_tb_wrapper
.rf_we_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_we_wb_i),
.rf_addr_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_waddr_wb_i),
.rf_wdata_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_wdata_wb_i),
.regfile_alu_we_ex_i(cv32e40px_top_i.core_i.id_stage_i.regfile_alu_we_ex_o),

// APU
.apu_req_i (cv32e40px_top_i.core_i.apu_req_o),
.apu_gnt_i (cv32e40px_top_i.core_i.apu_gnt_i),
.apu_rvalid_i(cv32e40px_top_i.core_i.apu_rvalid_i),
.apu_rvalid_i(cv32e40px_top_i.core_i.ex_stage_i.apu_valid),

// Controller FSM probes
.ctrl_fsm_cs_i(cv32e40px_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
Expand All @@ -355,6 +366,8 @@ module cv32e40px_tb_wrapper
.csr_we_i (cv32e40px_top_i.core_i.cs_registers_i.csr_we_int),
.csr_wdata_int_i(cv32e40px_top_i.core_i.cs_registers_i.csr_wdata_int),

.csr_fregs_we_i(cv32e40px_top_i.core_i.cs_registers_i.fregs_we_i),

.csr_mstatus_n_i (cv32e40px_top_i.core_i.cs_registers_i.mstatus_n),
.csr_mstatus_q_i (cv32e40px_top_i.core_i.cs_registers_i.mstatus_q),
.csr_mstatus_fs_n_i(cv32e40px_top_i.core_i.cs_registers_i.mstatus_fs_n),
Expand All @@ -367,6 +380,10 @@ module cv32e40px_tb_wrapper
.csr_tdata1_q_i (cv32e40px_top_i.core_i.cs_registers_i.tmatch_control_rdata),//gen_trigger_regs.tmatch_control_exec_q ),
.csr_tdata1_we_i(cv32e40px_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_control_we),

.csr_tdata2_n_i (cv32e40px_top_i.core_i.cs_registers_i.tmatch_value_rdata),//csr_wdata_int ),
.csr_tdata2_q_i (cv32e40px_top_i.core_i.cs_registers_i.tmatch_value_rdata),//gen_trigger_regs.tmatch_control_exec_q ),
.csr_tdata2_we_i(cv32e40px_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_value_we),

.csr_tinfo_n_i({16'h0, cv32e40px_top_i.core_i.cs_registers_i.tinfo_types}),
.csr_tinfo_q_i({16'h0, cv32e40px_top_i.core_i.cs_registers_i.tinfo_types}),

Expand Down Expand Up @@ -424,6 +441,7 @@ module cv32e40px_tb_wrapper
);
`endif


`ifdef CV32E40P_RVFI_TRACE_EXECUTION
bind cv32e40px_rvfi: rvfi_i cv32e40px_rvfi_trace #(
.FPU (FPU),
Expand Down
12 changes: 6 additions & 6 deletions bhv/include/cv32e40px_tracer_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -196,17 +196,17 @@ package cv32e40px_tracer_pkg;
parameter INSTR_CVEND0 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1};
parameter INSTR_CVCOUNTI0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1};
parameter INSTR_CVCOUNT0 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUPI0 = {12'b?, 5'b00000, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUP0 = {12'b?, 5'b00000, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUPI0 = {17'b?, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUP0 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1};

parameter INSTR_CVSTARTI1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVSTART1 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVSENDI1 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVEND1 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVCOUNTI1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVCOUNT1 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUPI1 = {12'b?, 5'b00000, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUP1 = {12'b?, 5'b00000, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUPI1 = {17'b?, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1};
parameter INSTR_CVSETUP1 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1};


parameter INSTR_FF1 = {7'b0100001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1};
Expand Down Expand Up @@ -449,8 +449,8 @@ package cv32e40px_tracer_pkg;
parameter INSTR_CVSHUFFLE2H = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
parameter INSTR_CVSHUFFLE2B = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};

parameter INSTR_CVPACK = {5'b11101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
parameter INSTR_CVPACKH = {5'b11101, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
parameter INSTR_CVPACK = {5'b11110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
parameter INSTR_CVPACKH = {5'b11110, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};

parameter INSTR_CVPACKHIB = {5'b11111, 1'b0, 1'b1, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
parameter INSTR_CVPACKLOB = {5'b11111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
Expand Down
201 changes: 103 additions & 98 deletions bhv/insn_trace.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,8 @@

int m_instret_cnt;

bit m_sample_csr_write_in_ex;

struct {
logic [31:0] addr ;
logic [ 3:0] rmask;
Expand Down Expand Up @@ -145,32 +147,33 @@


function new();
this.m_order = 0;
this.m_skip_order = 1'b0;
this.m_valid = 1'b0;
this.m_move_down_pipe = 1'b0;
this.m_data_missaligned = 1'b0;
this.m_got_first_data = 1'b0;
this.m_got_ex_reg = 1'b0;
this.m_intr = '0;
this.m_dbg_taken = 1'b0;
this.m_dbg_cause = '0;
this.m_is_ebreak = '0;
this.m_is_illegal = '0;
this.m_is_irq = '0;
this.m_is_memory = 1'b0;
this.m_is_load = 1'b0;
this.m_is_apu = 1'b0;
this.m_is_apu_ok = 1'b0;
this.m_apu_req_id = 0;
this.m_mem_req_id[0] = 0;
this.m_mem_req_id[1] = 0;
this.m_mem_req_id_valid = '0;
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
this.m_fcsr_we_non_apu = 1'b0;
this.m_instret_cnt = 0;
this.m_order = 0;
this.m_skip_order = 1'b0;
this.m_valid = 1'b0;
this.m_move_down_pipe = 1'b0;
this.m_data_missaligned = 1'b0;
this.m_got_first_data = 1'b0;
this.m_got_ex_reg = 1'b0;
this.m_intr = '0;
this.m_dbg_taken = 1'b0;
this.m_dbg_cause = '0;
this.m_is_ebreak = '0;
this.m_is_illegal = '0;
this.m_is_irq = '0;
this.m_is_memory = 1'b0;
this.m_is_load = 1'b0;
this.m_is_apu = 1'b0;
this.m_is_apu_ok = 1'b0;
this.m_apu_req_id = 0;
this.m_mem_req_id[0] = 0;
this.m_mem_req_id[1] = 0;
this.m_mem_req_id_valid = '0;
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
this.m_fcsr_we_non_apu = 1'b0;
this.m_instret_cnt = 0;
this.m_sample_csr_write_in_ex = 1'b1;
endfunction

function void get_mnemonic();
Expand Down Expand Up @@ -875,37 +878,38 @@
if(this.m_skip_order) begin
this.m_order = this.m_order + 64'h1;
end
this.m_skip_order = 1'b0;
this.m_pc_rdata = r_pipe_freeze_trace.pc_id;
this.m_is_illegal = 1'b0;
this.m_is_irq = 1'b0;
this.m_is_memory = 1'b0;
this.m_is_load = 1'b0;
this.m_is_apu = 1'b0;
this.m_is_apu_ok = 1'b0;
this.m_apu_req_id = 0;
this.m_mem_req_id[0] = 0;
this.m_mem_req_id[1] = 0;
this.m_mem_req_id_valid = '0;
this.m_data_missaligned = 1'b0;
this.m_got_first_data = 1'b0;
this.m_got_ex_reg = 1'b0;
this.m_got_regs_write = 1'b0;
this.m_move_down_pipe = 1'b0;
this.m_instret_cnt = 0;
this.m_rd_addr[0] = '0;
this.m_rd_addr[1] = '0;
this.m_2_rd_insn = 1'b0;
this.m_rs1_addr = '0;
this.m_rs2_addr = '0;
this.m_rs3_addr = '0;
this.m_ex_fw = '0;
this.m_csr.got_minstret = '0;
this.m_dbg_taken = '0;
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
this.m_fcsr_we_non_apu = 1'b0;
this.m_skip_order = 1'b0;
this.m_pc_rdata = r_pipe_freeze_trace.pc_id;
this.m_is_illegal = 1'b0;
this.m_is_irq = 1'b0;
this.m_is_memory = 1'b0;
this.m_is_load = 1'b0;
this.m_is_apu = 1'b0;
this.m_is_apu_ok = 1'b0;
this.m_apu_req_id = 0;
this.m_mem_req_id[0] = 0;
this.m_mem_req_id[1] = 0;
this.m_mem_req_id_valid = '0;
this.m_data_missaligned = 1'b0;
this.m_got_first_data = 1'b0;
this.m_got_ex_reg = 1'b0;
this.m_got_regs_write = 1'b0;
this.m_move_down_pipe = 1'b0;
this.m_instret_cnt = 0;
this.m_sample_csr_write_in_ex = 1'b1;
this.m_rd_addr[0] = '0;
this.m_rd_addr[1] = '0;
this.m_2_rd_insn = 1'b0;
this.m_rs1_addr = '0;
this.m_rs2_addr = '0;
this.m_rs3_addr = '0;
this.m_ex_fw = '0;
this.m_csr.got_minstret = '0;
this.m_dbg_taken = '0;
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
this.m_fcsr_we_non_apu = 1'b0;
this.m_csr.mcause_we = '0;
if (is_compressed_id_i) begin
this.m_insn[31:16] = '0;
Expand Down Expand Up @@ -944,47 +948,48 @@
endfunction

function void copy_full(insn_trace_t m_source);
this.m_valid = m_source.m_valid;
this.m_stage = m_source.m_stage;
this.m_order = m_source.m_order;
this.m_pc_rdata = m_source.m_pc_rdata;
this.m_insn = m_source.m_insn;
this.m_mnemonic = m_source.m_mnemonic;
this.m_is_memory = m_source.m_is_memory;
this.m_is_load = m_source.m_is_load;
this.m_is_apu = m_source.m_is_apu;
this.m_is_apu_ok = m_source.m_is_apu_ok;
this.m_apu_req_id = m_source.m_apu_req_id;
this.m_mem_req_id = m_source.m_mem_req_id;
this.m_mem_req_id_valid = m_source.m_mem_req_id_valid;
this.m_data_missaligned = m_source.m_data_missaligned;
this.m_got_first_data = m_source.m_got_first_data;
this.m_got_ex_reg = m_source.m_got_ex_reg;
this.m_dbg_taken = m_source.m_dbg_taken;
this.m_dbg_cause = m_source.m_dbg_cause;
this.m_is_ebreak = m_source.m_is_ebreak;
this.m_is_illegal = m_source.m_is_illegal;
this.m_is_irq = m_source.m_is_irq;
this.m_instret_cnt = m_source.m_instret_cnt;
this.m_rs1_addr = m_source.m_rs1_addr;
this.m_rs2_addr = m_source.m_rs2_addr;
this.m_rs3_addr = m_source.m_rs3_addr;
this.m_rs1_rdata = m_source.m_rs1_rdata;
this.m_rs2_rdata = m_source.m_rs2_rdata;
this.m_rs3_rdata = m_source.m_rs3_rdata;

this.m_ex_fw = m_source.m_ex_fw;
this.m_rd_addr = m_source.m_rd_addr;
this.m_2_rd_insn = m_source.m_2_rd_insn;
this.m_rd_wdata = m_source.m_rd_wdata;

this.m_intr = m_source.m_intr;
this.m_trap = m_source.m_trap;
this.m_fflags_we_non_apu = m_source.m_fflags_we_non_apu;
this.m_frm_we_non_apu = m_source.m_frm_we_non_apu ;
this.m_fcsr_we_non_apu = m_source.m_fcsr_we_non_apu;

this.m_mem = m_source.m_mem;
this.m_valid = m_source.m_valid;
this.m_stage = m_source.m_stage;
this.m_order = m_source.m_order;
this.m_pc_rdata = m_source.m_pc_rdata;
this.m_insn = m_source.m_insn;
this.m_mnemonic = m_source.m_mnemonic;
this.m_is_memory = m_source.m_is_memory;
this.m_is_load = m_source.m_is_load;
this.m_is_apu = m_source.m_is_apu;
this.m_is_apu_ok = m_source.m_is_apu_ok;
this.m_apu_req_id = m_source.m_apu_req_id;
this.m_mem_req_id = m_source.m_mem_req_id;
this.m_mem_req_id_valid = m_source.m_mem_req_id_valid;
this.m_data_missaligned = m_source.m_data_missaligned;
this.m_got_first_data = m_source.m_got_first_data;
this.m_got_ex_reg = m_source.m_got_ex_reg;
this.m_dbg_taken = m_source.m_dbg_taken;
this.m_dbg_cause = m_source.m_dbg_cause;
this.m_is_ebreak = m_source.m_is_ebreak;
this.m_is_illegal = m_source.m_is_illegal;
this.m_is_irq = m_source.m_is_irq;
this.m_instret_cnt = m_source.m_instret_cnt;
this.m_sample_csr_write_in_ex = m_source.m_sample_csr_write_in_ex;
this.m_rs1_addr = m_source.m_rs1_addr;
this.m_rs2_addr = m_source.m_rs2_addr;
this.m_rs3_addr = m_source.m_rs3_addr;
this.m_rs1_rdata = m_source.m_rs1_rdata;
this.m_rs2_rdata = m_source.m_rs2_rdata;
this.m_rs3_rdata = m_source.m_rs3_rdata;

this.m_ex_fw = m_source.m_ex_fw;
this.m_rd_addr = m_source.m_rd_addr;
this.m_2_rd_insn = m_source.m_2_rd_insn;
this.m_rd_wdata = m_source.m_rd_wdata;

this.m_intr = m_source.m_intr;
this.m_trap = m_source.m_trap;
this.m_fflags_we_non_apu = m_source.m_fflags_we_non_apu;
this.m_frm_we_non_apu = m_source.m_frm_we_non_apu ;
this.m_fcsr_we_non_apu = m_source.m_fcsr_we_non_apu;

this.m_mem = m_source.m_mem;
//CRS
`ASSIGN_CSR(mstatus)
`ASSIGN_CSR(mstatus_fs)
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