Bubblesort

This VHDL project implements the bubblesort algorithm and it's respective testbench. It requires, but doesn't include (due to copyright), a RAM entity that conforms to:

generic(
   dataWidth: positive := 8;
   addressWidth: positive := 8
);
port(
   address_a: in std_logic_vector (addressWidth-1 downto 0);
   address_b: in std_logic_vector (addressWidth-1 downto 0);
   clock: in std_logic  := '1';
   data_a: in std_logic_vector (dataWidth-1 downto 0);
   data_b: in std_logic_vector (dataWidth-1 downto 0);
   wren_a: in std_logic  := '0';
   wren_b: in std_logic  := '0';
   q_a: out std_logic_vector (dataWidth-1 downto 0);
   q_b: out std_logic_vector (dataWidth-1 downto 0)
);

I used the one generated by Quartus, from Intel. Finally, since this was realized as part of the computer science course in a Brazilian university, it is partially written in portuguese.