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Merge branch 'devel'
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guilhermerc committed Oct 24, 2022
2 parents b038658 + 245d7a2 commit e40c2ef
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116 changes: 60 additions & 56 deletions hdl/modules/position_calc/position_calc.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -425,7 +425,7 @@ architecture rtl of position_calc is
signal valid_tbt, valid_tbt_cordic, valid_fofb, valid_fofb_cordic, valid_monit1, valid_monit2 : ce_sl := (others => '0');
signal ce_adc, ce_monit1, ce_monit2, ce_tbt_cordic, ce_fofb_cordic : ce_sl := (others => '0');

signal valid_monit1_ds, valid_fofb_ds, valid_tbt_ds : std_logic;
signal valid_monit1_pds, valid_fofb_pds, valid_tbt_ds : std_logic;

attribute max_fanout : string;
attribute max_fanout of ce_adc, ce_monit1, ce_monit2 : signal is "50";
Expand Down Expand Up @@ -794,65 +794,69 @@ begin

end generate gen_ddc;

-- x, y, and q are fixed point with:
-- x and y are fixed point with:
-- sign bit = MSB
-- word length = g_width
-- integer length = g_k_width + 1
-- fractional length = g_width - (integer length)
cmp_fofb_ds : delta_sigma
-- word length = g_WIDTH
-- integer length = g_K_WIDTH
-- fractional length = g_WIDTH - g_K_WIDTH
cmp_fofb_pds : part_delta_sigma
generic map (
g_width => g_fofb_decim_width,
g_k_width => g_k_width,
g_offset_width => g_offset_width)
g_WIDTH => g_FOFB_DECIM_WIDTH,
g_K_WIDTH => g_K_WIDTH,
g_OFFSET_WIDTH => g_OFFSET_WIDTH
)
port map (
a_i => fofb_mag(0),
b_i => fofb_mag(1),
c_i => fofb_mag(2),
d_i => fofb_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
clk_i => clk_i,
ce_i => ce_fofb_cordic(0),
valid_i => valid_fofb_cordic(0),
valid_o => valid_fofb_ds,
rst_i => rst_i,
x_o => fofb_pos_x_int,
y_o => fofb_pos_y_int,
q_o => fofb_pos_q_int,
sum_o => fofb_pos_sum_int);

-- x, y, and q are fixed point with:
clk_i => clk_i,
rst_i => rst_i,
a_i => fofb_mag(0),
b_i => fofb_mag(1),
c_i => fofb_mag(2),
d_i => fofb_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
ce_i => ce_fofb_cordic(0),
valid_i => valid_fofb_cordic(0),
x_o => fofb_pos_x_int,
y_o => fofb_pos_y_int,
q_o => fofb_pos_q_int,
sum_o => fofb_pos_sum_int,
valid_o => valid_fofb_pds
);

-- x and y are fixed point with:
-- sign bit = MSB
-- word length = g_width
-- integer length = g_k_width + 1
-- fractional length = g_width - (integer length)
cmp_monit1_ds : delta_sigma
-- word length = g_WIDTH
-- integer length = g_K_WIDTH
-- fractional length = g_WIDTH - g_K_WIDTH
cmp_monit1_pds : part_delta_sigma
generic map (
g_width => g_monit_decim_width,
g_k_width => g_k_width,
g_offset_width => g_offset_width)
g_WIDTH => g_MONIT_DECIM_WIDTH,
g_K_WIDTH => g_K_WIDTH,
g_OFFSET_WIDTH => g_OFFSET_WIDTH
)
port map (
a_i => monit1_mag(0),
b_i => monit1_mag(1),
c_i => monit1_mag(2),
d_i => monit1_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
clk_i => clk_i,
ce_i => ce_monit1(0),
valid_i => valid_monit1(0),
valid_o => valid_monit1_ds,
rst_i => rst_i,
x_o => monit1_pos_x_int,
y_o => monit1_pos_y_int,
q_o => monit1_pos_q_int,
sum_o => monit1_pos_sum_int);
clk_i => clk_i,
rst_i => rst_i,
a_i => monit1_mag(0),
b_i => monit1_mag(1),
c_i => monit1_mag(2),
d_i => monit1_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
ce_i => ce_monit1(0),
valid_i => valid_monit1(0),
x_o => monit1_pos_x_int,
y_o => monit1_pos_y_int,
q_o => monit1_pos_q_int,
sum_o => monit1_pos_sum_int,
valid_o => valid_monit1_pds
);

-- desync counters. Use only one of the channels as a sample
tbt_tag_desync_cnt_o <= tbt_tag_desync_cnt(0);
Expand Down Expand Up @@ -937,7 +941,7 @@ begin
monit_amp_valid_o <= valid_monit2(0);
monit_amp_ce_o <= ce_monit2(0);

fofb_pos_valid_o <= valid_fofb_ds;
fofb_pos_valid_o <= valid_fofb_pds;
fofb_pos_ce_o <= ce_fofb_cordic(0);

fofb_pos_x_o <= std_logic_vector(shift_right(signed(fofb_pos_x_int), g_fofb_decim_width-g_k_width));
Expand All @@ -954,7 +958,7 @@ begin
tbt_pos_q_o <= (others => '0');
tbt_pos_sum_o <= (others => '0');

monit1_pos_valid_o <= valid_monit1_ds;
monit1_pos_valid_o <= valid_monit1_pds;
monit1_pos_ce_o <= ce_monit1(0);

monit1_pos_x_o <= std_logic_vector(shift_right(signed(monit1_pos_x_int), g_monit_decim_width-g_k_width));
Expand Down
20 changes: 10 additions & 10 deletions hdl/syn/gen_sdbsyn.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#!/usr/bin/python
#!/usr/bin/python3

##-----------------------------------------------------------------------------
## Title : SDB Synthesis info autogen
Expand Down Expand Up @@ -90,7 +90,7 @@ def write_sdb_info(f, r_name, m_name, commit, dirty, tool, toolv, date, user):
def git_username():
# gets username from git config
temp = subprocess.Popen("git config user.name", stdout=subprocess.PIPE, shell=True)
user = temp.stdout.read().split()
user = temp.stdout.read().decode('utf-8').split()
if len(user) == 1:
#is a single word, so we just use it
return user[0]
Expand All @@ -115,48 +115,48 @@ def main():
#######

temp = subprocess.Popen("git rev-parse --show-toplevel", stdout=subprocess.PIPE, shell=True)
toplevel = temp.stdout.read()[0:-1] #remove trailing \n
toplevel = temp.stdout.read().decode('utf-8')[0:-1] #remove trailing \n
f = open(args.o + PKG_FILE, 'w')
f.write(PKG_HEADER)
### Make the first constant which is repo url
f.write(REPO_URL)
temp = subprocess.Popen("git config remote.origin.url", stdout=subprocess.PIPE, shell=True)
url = temp.stdout.read()[0:-1]
url = temp.stdout.read().decode("utf-8")[0:-1]
f.write(SDB_URL + " => \"" + url[:URL_LEN].ljust(URL_LEN) + "\");\n") #truncate or expand string

### Now generate synthesis info for main repository
# get commit id
temp = subprocess.Popen("git log --always --pretty=format:'%H' -n 1", stdout=subprocess.PIPE, shell=True)
commit_id = temp.stdout.read()[:32]
commit_id = temp.stdout.read().decode('utf-8')[:32]
dirty = False
temp = subprocess.Popen(GIT_DIRTY, stdout=subprocess.PIPE, shell=True)
if temp.stdout.read()[-2] == '+':
if temp.stdout.read().decode('utf-8')[-2] == '+':
dirty = True #commit_id = commit_id + '+'
# get date
day = datetime.datetime.today().day
mon = datetime.datetime.today().month
year = datetime.datetime.today().year
date = int(str(year*10000 + mon*100 + day), 16) # strange, I know, but I want to have something like x"20140917"
# convert version
ver = int(args.ver.translate(None, '.,'), 16)
ver = int(args.ver.translate(str.maketrans(dict.fromkeys('.,'))), 16)
# fill this all to the structure
write_sdb_info(f, MAIN_SYN, args.project, commit_id, dirty, args.tool, ver, date, args.user)

### Now generate synthesis info for each submodule
temp = subprocess.Popen("(cd "+toplevel+"; git submodule status)", stdout=subprocess.PIPE, shell=True)
submodules = temp.stdout.read()
submodules = temp.stdout.read().decode('utf-8')
submodules = submodules.split('\n')
for module in submodules[:-1]:
mod_splited = module.split()
name = mod_splited[1].split('/')[-1]
# if submodule is ahead of a set commit it displays additional _+_ at the
# beginning, get rid of that:
commit_id = mod_splited[0].translate(None, '+')[:32]
commit_id = mod_splited[0].translate(str.maketrans(dict.fromkeys('+')))[:32]
# check if dirty
dirty = False
temp = subprocess.Popen("(cd "+toplevel+"/"+mod_splited[1]+ ";" + GIT_DIRTY +")",
stdout=subprocess.PIPE, shell=True)
if temp.stdout.read()[-2] == '+':
if temp.stdout.read().decode('utf-8')[-2] == '+':
dirty = True
write_sdb_info(f, name, name, commit_id, dirty, " ", 0, 0, " ")

Expand Down

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