[CodeGen] Really renumber slot indexes before register allocation #67038
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@llvm/pr-subscribers-llvm-transforms @llvm/pr-subscribers-backend-aarch64 ChangesPR #66334 tried to renumber slot indexes before register allocation, but Patch is 38.80 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/67038.diff 693 Files Affected:
diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp
index 65726f06dedb473..f0cb187a2574256 100644
--- a/llvm/lib/CodeGen/SlotIndexes.cpp
+++ b/llvm/lib/CodeGen/SlotIndexes.cpp
@@ -238,8 +238,27 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
}
void SlotIndexes::packIndexes() {
- for (auto [Index, Entry] : enumerate(indexList))
- Entry.setIndex(Index * SlotIndex::InstrDist);
+ unsigned Index = 0;
+ // Iterate over basic blocks in slot index order.
+ for (MachineBasicBlock *MBB : make_second_range(idx2MBBMap)) {
+ // Update entries for each instruction in the block and the dummy entry for
+ // the end of the block.
+ auto [MBBStartIdx, MBBEndIdx] = MBBRanges[MBB->getNumber()];
+ for (auto I = MBBStartIdx.listEntry()->getIterator(),
+ E = MBBEndIdx.listEntry()->getIterator();
+ I++ != E;) {
+ if (I == E || I->getInstr()) {
+ Index += SlotIndex::InstrDist;
+ I->setIndex(Index);
+ } else {
+ // LiveIntervals may still refer to entries for instructions that have
+ // been erased. We have to update these entries but we don't want them
+ // to affect the rest of the slot numbering, so set them to half way
+ // between the neighboring real instrucion indexes.
+ I->setIndex(Index + SlotIndex::InstrDist / 2);
+ }
+ }
+ }
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
index fb4bef33d9b4ffd..348528f02d93217 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
@@ -236,8 +236,8 @@ define dso_local i128 @load_atomic_i128_aligned_unordered(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_unordered:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}
@@ -251,8 +251,8 @@ define dso_local i128 @load_atomic_i128_aligned_unordered_const(ptr readonly %pt
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_unordered_const:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}
@@ -266,8 +266,8 @@ define dso_local i128 @load_atomic_i128_aligned_monotonic(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_monotonic:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}
@@ -281,8 +281,8 @@ define dso_local i128 @load_atomic_i128_aligned_monotonic_const(ptr readonly %pt
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_monotonic_const:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}
@@ -296,8 +296,8 @@ define dso_local i128 @load_atomic_i128_aligned_acquire(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_acquire:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}
@@ -311,8 +311,8 @@ define dso_local i128 @load_atomic_i128_aligned_acquire_const(ptr readonly %ptr)
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_acquire_const:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}
@@ -326,8 +326,8 @@ define dso_local i128 @load_atomic_i128_aligned_seq_cst(ptr %ptr) {
; -O0: stlxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_seq_cst:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stlxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stlxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}
@@ -341,8 +341,8 @@ define dso_local i128 @load_atomic_i128_aligned_seq_cst_const(ptr readonly %ptr)
; -O0: stlxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_seq_cst_const:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stlxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stlxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc.ll
index 373b040ebec65d1..c5c03cbb0763119 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc.ll
@@ -236,8 +236,8 @@ define dso_local i128 @load_atomic_i128_aligned_unordered(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_unordered:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}
@@ -251,8 +251,8 @@ define dso_local i128 @load_atomic_i128_aligned_unordered_const(ptr readonly %pt
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_unordered_const:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}
@@ -266,8 +266,8 @@ define dso_local i128 @load_atomic_i128_aligned_monotonic(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_monotonic:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}
@@ -281,8 +281,8 @@ define dso_local i128 @load_atomic_i128_aligned_monotonic_const(ptr readonly %pt
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_monotonic_const:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}
@@ -296,8 +296,8 @@ define dso_local i128 @load_atomic_i128_aligned_acquire(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_acquire:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}
@@ -311,8 +311,8 @@ define dso_local i128 @load_atomic_i128_aligned_acquire_const(ptr readonly %ptr)
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_acquire_const:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}
@@ -326,8 +326,8 @@ define dso_local i128 @load_atomic_i128_aligned_seq_cst(ptr %ptr) {
; -O0: stlxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_seq_cst:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stlxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stlxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}
@@ -341,8 +341,8 @@ define dso_local i128 @load_atomic_i128_aligned_seq_cst_const(ptr readonly %ptr)
; -O0: stlxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_seq_cst_const:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stlxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stlxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-v8a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-v8a.ll
index 045e080983d5f89..0368ec909e53639 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-v8a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-v8a.ll
@@ -236,8 +236,8 @@ define dso_local i128 @load_atomic_i128_aligned_unordered(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_unordered:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}
@@ -251,8 +251,8 @@ define dso_local i128 @load_atomic_i128_aligned_unordered_const(ptr readonly %pt
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_unordered_const:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}
@@ -266,8 +266,8 @@ define dso_local i128 @load_atomic_i128_aligned_monotonic(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_monotonic:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}
@@ -281,8 +281,8 @@ define dso_local i128 @load_atomic_i128_aligned_monotonic_const(ptr readonly %pt
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_monotonic_const:
-; -O1: ldxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}
@@ -296,8 +296,8 @@ define dso_local i128 @load_atomic_i128_aligned_acquire(ptr %ptr) {
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_acquire:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}
@@ -311,8 +311,8 @@ define dso_local i128 @load_atomic_i128_aligned_acquire_const(ptr readonly %ptr)
; -O0: stxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_acquire_const:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}
@@ -326,8 +326,8 @@ define dso_local i128 @load_atomic_i128_aligned_seq_cst(ptr %ptr) {
; -O0: stlxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_seq_cst:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stlxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stlxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}
@@ -341,8 +341,8 @@ define dso_local i128 @load_atomic_i128_aligned_seq_cst_const(ptr readonly %ptr)
; -O0: stlxp w8, x0, x1, [x9]
;
; -O1-LABEL: load_atomic_i128_aligned_seq_cst_const:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: stlxp w9, x0, x1, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: stlxp w9, x8, x1, [x0]
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
index 0c52a8a683e3a06..55d48f1bd6226b1 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
@@ -156,8 +156,8 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O0: subs w8, w9, w8
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
-; -O1: ldxr w0, [x8]
-; -O1: stxr w9, w1, [x8]
+; -O1: ldxr w8, [x0]
+; -O1: stxr w9, w1, [x0]
%r = atomicrmw xchg ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
}
@@ -170,8 +170,8 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0: subs w8, w9, w8
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acquire:
-; -O1: ldaxr w0, [x8]
-; -O1: stxr w9, w1, [x8]
+; -O1: ldaxr w8, [x0]
+; -O1: stxr w9, w1, [x0]
%r = atomicrmw xchg ptr %ptr, i32 %value acquire, align 4
ret i32 %r
}
@@ -184,8 +184,8 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0: subs w8, w9, w8
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_release:
-; -O1: ldxr w0, [x8]
-; -O1: stlxr w9, w1, [x8]
+; -O1: ldxr w8, [x0]
+; -O1: stlxr w9, w1, [x0]
%r = atomicrmw xchg ptr %ptr, i32 %value release, align 4
ret i32 %r
}
@@ -198,8 +198,8 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0: subs w8, w9, w8
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
-; -O1: ldaxr w0, [x8]
-; -O1: stlxr w9, w1, [x8]
+; -O1: ldaxr w8, [x0]
+; -O1: stlxr w9, w1, [x0]
%r = atomicrmw xchg ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
}
@@ -212,8 +212,8 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0: subs w8, w9, w8
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
-; -O1: ldaxr w0, [x8]
-; -O1: stlxr w9, w1, [x8]
+; -O1: ldaxr w8, [x0]
+; -O1: stlxr w9, w1, [x0]
%r = atomicrmw xchg ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
}
@@ -226,8 +226,8 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
-; -O1: ldxr x0, [x8]
-; -O1: stxr w9, x1, [x8]
+; -O1: ldxr x8, [x0]
+; -O1: stxr w9, x1, [x0]
%r = atomicrmw xchg ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
}
@@ -240,8 +240,8 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acquire:
-; -O1: ldaxr x0, [x8]
-; -O1: stxr w9, x1, [x8]
+; -O1: ldaxr x8, [x0]
+; -O1: stxr w9, x1, [x0]
%r = atomicrmw xchg ptr %ptr, i64 %value acquire, align 8
ret i64 %r
}
@@ -254,8 +254,8 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_release:
-; -O1: ldxr x0, [x8]
-; -O1: stlxr w9, x1, [x8]
+; -O1: ldxr x8, [x0]
+; -O1: stlxr w9, x1, [x0]
%r = atomicrmw xchg ptr %ptr, i64 %value release, align 8
ret i64 %r
}
@@ -268,8 +268,8 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
-; -O1: ldaxr x0, [x8]
-; -O1: stlxr w9, x1, [x8]
+; -O1: ldaxr x8, [x0]
+; -O1: stlxr w9, x1, [x0]
%r = atomicrmw xchg ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
}
@@ -282,8 +282,8 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
-; -O1: ldaxr x0, [x8]
-; -O1: stlxr w9, x1, [x8]
+; -O1: ldaxr x8, [x0]
+; -O1: stlxr w9, x1, [x0]
%r = atomicrmw xchg ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
}
@@ -852,9 +852,9 @@ define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_add_i64_aligned_monotonic:
-; -O1: ldxr x0, [x8]
-; -O1: add x9, x0, x1
-; -O1: stxr w10, x9, [x8]
+; -O1: ldxr x8, [x0]
+; -O1: add x9, x8, x1
+; -O1: stxr w10, x9, [x0]
%r = atomicrmw add ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
}
@@ -868,9 +868,9 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acquire:
-; -O1: ldaxr x0, [x8]
-; -O1: add x9, x0, x1
-; -O1: stxr w10, x9, [x8]
+; -O1: ldaxr x8, [x0]
+; -O1: add x9, x8, x1
+; -O1: stxr w10, x9, [x0]
%r = atomicrmw add ptr %ptr, i64 %value acquire, align 8
ret i64 %r
}
@@ -884,9 +884,9 @@ define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_add_i64_aligned_release:
-; -O1: ldxr x0, [x8]
-; -O1: add x9, x0, x1
-; -O1: stlxr w10, x9, [x8]
+; -O1: ldxr x8, [x0]
+; -O1: add x9, x8, x1
+; -O1: stlxr w10, x9, [x0]
%r = atomicrmw add ptr %ptr, i64 %value release, align 8
ret i64 %r
}
@@ -900,9 +900,9 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acq_rel:
-; -O1: ldaxr x0, [x8]
-; -O1: add x9, x0, x1
-; -O1: stlxr w10, x9, [x8]
+; -O1: ldaxr x8, [x0]
+; -O1: add x9, x8, x1
+; -O1: stlxr w10, x9, [x0]
%r = atomicrmw add ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
}
@@ -916,9 +916,9 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_add_i64_aligned_seq_cst:
-; -O1: ldaxr x0, [x8]
-; -O1: add x9, x0, x1
-; -O1: stlxr w10, x9, [x8]
+; -O1: ldaxr x8, [x0]
+; -O1: add x9, x8, x1
+; -O1: stlxr w10, x9, [x0]
%r = atomicrmw add ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
}
@@ -939,9 +939,9 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
; -O0: subs x8, x8, #0
;
; -O1-LABEL: atomicrmw_add_i128_aligned_monotonic:
-; -O1: ldxp x0, x1, [x8]
-; -O1: adds x9, x0, x2
-; -O1: stxp w11, x9, x10, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: adds x9, x8, x2
+; -O1: stxp w11, x9, x10, [x0]
%r = atomicrmw add ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
}
@@ -962,9 +962,9 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O0: subs x8, x8, #0
;
; -O1-LABEL: atomicrmw_add_i128_aligned_acquire:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: adds x9, x0, x2
-; -O1: stxp w11, x9, x10, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: adds x9, x8, x2
+; -O1: stxp w11, x9, x10, [x0]
%r = atomicrmw add ptr %ptr, i128 %value acquire, align 16
ret i128 %r
}
@@ -985,9 +985,9 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
; -O0: subs x8, x8, #0
;
; -O1-LABEL: atomicrmw_add_i128_aligned_release:
-; -O1: ldxp x0, x1, [x8]
-; -O1: adds x9, x0, x2
-; -O1: stlxp w11, x9, x10, [x8]
+; -O1: ldxp x8, x1, [x0]
+; -O1: adds x9, x8, x2
+; -O1: stlxp w11, x9, x10, [x0]
%r = atomicrmw add ptr %ptr, i128 %value release, align 16
ret i128 %r
}
@@ -1008,9 +1008,9 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O0: subs x8, x8, #0
;
; -O1-LABEL: atomicrmw_add_i128_aligned_acq_rel:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: adds x9, x0, x2
-; -O1: stlxp w11, x9, x10, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: adds x9, x8, x2
+; -O1: stlxp w11, x9, x10, [x0]
%r = atomicrmw add ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
}
@@ -1031,9 +1031,9 @@ define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value)
; -O0: subs x8, x8, #0
;
; -O1-LABEL: atomicrmw_add_i128_aligned_seq_cst:
-; -O1: ldaxp x0, x1, [x8]
-; -O1: adds x9, x0, x2
-; -O1: stlxp w11, x9, x10, [x8]
+; -O1: ldaxp x8, x1, [x0]
+; -O1: adds x9, x8, x2
+; -O1: stlxp w11, x9, x10, [x0]
%r = atomicrmw add ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
}
@@ -1632,9 +1632,9 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x8, x9, x8
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_monotonic:
-; -O1: ldxr x0, [x8]
-; -O1: sub x9, x0, x1
-; -O1: stxr w10, x9, [x8]
+; -O1: ldxr x8, [x0]
+; -O1: sub x9, x8, x1
+; -O1: stxr w10, x9, [x0]
%r = atomicr...
[truncated]
|
|
TODO: update 33 failing tests with manual checks. |
|
MSP430 test changes seems to be fine |
perlfu
reviewed
Sep 22, 2023
jayfoad
added a commit
that referenced
this pull request
Sep 28, 2023
This makes some tests robust against minor codegen differences that will be caused by PR #67038.
|
Rebased and fixed almost all lit tests. (Sorry for the force push but quite a few lit tests conflicted with other upstream changes since this PR was opened.) I might need help with the last two lit test failures: |
legrosbuffle
pushed a commit
to legrosbuffle/llvm-project
that referenced
this pull request
Sep 29, 2023
This makes some tests robust against minor codegen differences that will be caused by PR llvm#67038.
blackgeorge-boom
added a commit
to blackgeorge-boom/llvm-project
that referenced
this pull request
Sep 29, 2023
Applies: llvm#66334 llvm#67038 Packing the slot indexes before register allocation is useful for us because it evens the gaps between slots after all the optimization passes that happen before `greedy` and may have removed a different number of instructions between AArch64 and X86. This leads to different slot gaps and, hence, slightly different regalloc in some cases. We backport the above patches for our LLVM, with the main difference being the absence of some convenient data structure iterators, which we had to convert to be compatible with our ADT infrastructure. We add the `-pack-indexes` flag to activate this. Addressses: systems-nuts/unifico#291
Hi @kparzysz-quic, could you help with these please? The code changes quite a bit, so I'm not even sure if they are still testing what they were supposed to test. |
|
@jayfoad I'd suggest marking those tests as XFAIL, to avoid further bitrot. |
Done, thanks. |
|
Any more comments? If not I will plan to merge this on Monday, based on @qcolombet's approval. |
PR #66334 tried to renumber slot indexes before register allocation, but the numbering was still affected by list entries for instructions which had been erased. Fix this to make the register allocator's live range length heuristics even less dependent on the history of how instructions have been added to and removed from SlotIndexes's maps.
jayfoad
added a commit
to jayfoad/llvm-project
that referenced
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Jan 29, 2024
Add a basic implementation of verifyAnalysis that just checks that the analysis does not refer to any SlotIndexes for instructions that have been deleted. This was useful for diagnosing some SlotIndexes-related problems caused by llvm#67038.
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PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries for instructions which
had been erased. Fix this to make the register allocator's live range
length heuristics even less dependent on the history of how instructions
have been added to and removed from SlotIndexes's maps.