GitHub - jaesparza/MScThesis: My M.Sc. thesis: "A VMD-RT Methodology for the Hw/Sw Co-Design of Embedded Systems". The repository hosts VDM++, VDM-RT and UML models as well as the full thesis.

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My M.Sc. thesis: "A VMD-RT Methodology for the Hw/Sw Co-Design of Embedded Systems". The repository hosts VDM++, VDM-RT and UML models as well as the full thesis.

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
UMLmodels		UMLmodels
VDMmodels		VDMmodels
.gitattributes		.gitattributes
.gitignore		.gitignore
awardIngenioeren.PNG		awardIngenioeren.PNG
thesisReport.pdf		thesisReport.pdf

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My M.Sc. thesis: "A VMD-RT Methodology for the Hw/Sw Co-Design of Embedded Systems". The repository hosts VDM++, VDM-RT and UML models as well as the full thesis.

embedded-systems modelling vdmpp vdmrt hardware-software-design

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