Roger enable pm for ish5p8

bsp_sedi/soc/intel_ish/include/sedi_soc_regs.h

@@ -115,9 +115,15 @@ SEDI_IREG_BASE_DEFINE(IPC, PMC, 0x4111000);
 #define SEDI_PMU_BASE (0x04200000)
 #define SEDI_CCU_BASE 0x04300000
 
+#ifdef CONFIG_SOC_INTEL_ISH_5_8_0
+#define SEDI_IRQ_RESET_PREP (8)
+#define SEDI_IRQ_PCIEDEV (11)
+#define SEDI_IRQ_PMU2IOAPIC (12)
+#else
 #define SEDI_IRQ_RESET_PREP (6)
 #define SEDI_IRQ_PCIEDEV (9)
 #define SEDI_IRQ_PMU2IOAPIC (10)
+#endif
 
 /****** APIC *****/
 #define SEDI_IOAPIC_BASE 0xFEC00000

bsp_sedi/soc/intel_ish/pm/aon/aon_task.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 Intel Corporation
+ * Copyright (c) 2023-2024 Intel Corporation
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -312,7 +312,11 @@ static int restore_main_fw(void)
 
 /* SRAM needs time to enter retention mode */
 #define CYCLES_PER_US                  100
+#ifdef CONFIG_SOC_INTEL_ISH_5_8_0
+#define SRAM_RETENTION_US_DELAY	       20
+#else
 #define SRAM_RETENTION_US_DELAY	       5
+#endif
 #define SRAM_RETENTION_CYCLES_DELAY    (SRAM_RETENTION_US_DELAY * CYCLES_PER_US)
 
 #ifdef CONFIG_SOC_INTEL_ISH_5_6_0
@@ -384,16 +388,34 @@ static void sram_power(int on)
 
 /**
  * check SRAM bank i power gated status in PMU_SRAM_PG_EN register
+ * 2 bits for one bank on ISH5.8, 1 bit on ISH5.4
  * 1: power gated 0: not power gated
  */
-#define BANK_PG_STATUS(i)	(read32(PMU_SRAM_PG_EN) & (0x1 << (i)))
+#ifndef CONFIG_SOC_INTEL_ISH_5_8_0
+/* SRAM needs time to warm up after power on */
+#define SRAM_WARM_UP_DELAY_CNT		10
+#define SRAM_PG_BITS(i) (1 << i)
+#else
+/* SRAM needs time to warm up after power on */
+#define SRAM_WARM_UP_DELAY_CNT		2000
+#define SRAM_PG_BITS(i) (0x3 << (2 * i))
+/**
+ * check SRAM bank i power status in PMU_SRAM_PWR_STATUS register
+ * one bank has two tiles, 2 bits for one bank
+ * 1: ready for operation 0: not ready for operation
+ */
+#define BANK_PWR_STATUS(i) (read32(PMU_SRAM_PWR_STATUS) & SRAM_PG_BITS(i))
+#endif
+
+#define BANK_PG_STATUS(i)	(read32(PMU_SRAM_PG_EN) & SRAM_PG_BITS(i))
 
 /* enable power gate of a SRAM bank */
-#define BANK_PG_ENABLE(i)	(write32(PMU_SRAM_PG_EN, (read32(PMU_SRAM_PG_EN) | (0x1 << (i)))))
+#define BANK_PG_ENABLE(i) \
+	(write32(PMU_SRAM_PG_EN, (read32(PMU_SRAM_PG_EN) | SRAM_PG_BITS(i))))
 
 /* disable power gate of a SRAM bank */
-#define BANK_PG_DISABLE(i)                                                     \
-	(write32(PMU_SRAM_PG_EN, (read32(PMU_SRAM_PG_EN) & (~(0x1 << (i))))))
+#define BANK_PG_DISABLE(i) \
+	(write32(PMU_SRAM_PG_EN, (read32(PMU_SRAM_PG_EN) & (~SRAM_PG_BITS(i)))))
 
 /**
  * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register
@@ -411,9 +433,6 @@ static void sram_power(int on)
 	(write32(ISH_SRAM_CTRL_CSFGR,                                          \
 		 (read32(ISH_SRAM_CTRL_CSFGR) | (0x1 << ((i) + 4)))))
 
-/* SRAM needs time to warm up after power on */
-#define SRAM_WARM_UP_DELAY_CNT		10
-
 static void sram_power(int on)
 {
 	int i;
@@ -433,11 +452,15 @@ static void sram_power(int on)
 
 	for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) {
 
-		if (on && (BANK_PG_STATUS(i))) {
+		if (on) {
 
 			/* power on and enable a bank */
 			BANK_PG_DISABLE(i);
 
+#ifdef CONFIG_SOC_INTEL_ISH_5_8_0
+			while (!BANK_PWR_STATUS(i))
+				;
+#endif
 			delay(SRAM_WARM_UP_DELAY_CNT);
 
 			/* erase a bank */
@@ -451,6 +474,12 @@ static void sram_power(int on)
 		} else {
 			/* disable and power off a bank */
 			BANK_PG_ENABLE(i);
+
+#ifdef CONFIG_SOC_INTEL_ISH_5_8_0
+			while (BANK_PWR_STATUS(i))
+				;
+#endif
+			delay(SRAM_WARM_UP_DELAY_CNT);
 		}
 
 		/**
@@ -565,65 +594,91 @@ static inline void clear_vnnred_aoncg(void)
 	write32(CCU_AONCG_EN, 0);
 }
 
-#ifdef CONFIG_SOC_INTEL_ISH_5_6_0
-#define STRINGIFY(x)			#x
-#define SLINE(num)			STRINGIFY(num)
-#define RETENTION_EXIT_CYCLES_DELAY	5
+/* SRAM needs 5 clock cycles to avoid power strike when out of retention */
+#define RETENTION_EXTRA_CYCLES_DELAY (5)
+
+#ifdef CONFIG_SOC_INTEL_ISH_5_8_0
+/* enable deep sleep of a SRAM bank */
+#define BANK_DS_ENABLE(i) \
+	(write32(PMU_SRAM_DEEPSLEEP, read32(PMU_SRAM_DEEPSLEEP) | (0x3 << (2 * i))))
+
+/* disable deep sleep of a SRAM bank */
+#define BANK_DS_DISABLE(i) \
+	(write32(PMU_SRAM_DEEPSLEEP, read32(PMU_SRAM_DEEPSLEEP) & ~(0x3 << (2 * i))))
 
-static void sram_enter_sleep_mode(void)
+/**
+ * check SRAM bank i power status in PMU_SRAM_PWR_STATUS register
+ * one bank has two tiles, 2 bit for one bank
+ * 1: ready for operation 0: not ready for operation
+ */
+#define BANK_PWR_STATUS(i) (read32(PMU_SRAM_PWR_STATUS) & (0x3 << (2 * i)))
+#endif
+
+static void sram_retention(int out)
 {
+#if defined(CONFIG_SOC_INTEL_ISH_5_6_0)
 	uint32_t val, sum_mask, mask;
 
 	sum_mask = mask = 0x1;
 	val = read32(PMU_SRAM_DEEPSLEEP);
 	while (sum_mask <= CONFIG_RAM_BANK_TILE_MASK) {
-		if (!(val & mask)) {
-			write32(PMU_SRAM_DEEPSLEEP, val | sum_mask);
-			while (read32(PMU_SRAM_PWR_STATUS) & mask)
-				;
+		if (out) {
+			if ((val & mask)) {
+				write32(PMU_SRAM_DEEPSLEEP, val & ~sum_mask);
+				while (!(read32(PMU_SRAM_PWR_STATUS) & mask))
+					;
+				delay(RETENTION_EXTRA_CYCLES_DELAY);
+			}
+		} else {
+			if (!(val & mask)) {
+				write32(PMU_SRAM_DEEPSLEEP, val | sum_mask);
+				while (read32(PMU_SRAM_PWR_STATUS) & mask)
+					;
+			}
 		}
 		mask <<= 1;
 		sum_mask += mask;
 	}
-}
-
-static void sram_exit_sleep_mode(void)
-{
-	uint32_t val, sum_mask, mask;
-
-	sum_mask = mask = 0x1;
-	val = read32(PMU_SRAM_DEEPSLEEP);
-	while (sum_mask <= CONFIG_RAM_BANK_TILE_MASK) {
-		if ((val & mask)) {
-			write32(PMU_SRAM_DEEPSLEEP, val & ~sum_mask);
-			while (!(read32(PMU_SRAM_PWR_STATUS) & mask))
+#elif defined(CONFIG_SOC_INTEL_ISH_5_8_0)
+	for (int i = 0; i < SRAM_POWER_OFF_BANKS; i++) {
+		if (out && !BANK_PWR_STATUS(i)) {
+			/* exit deep sleep on a bank */
+			BANK_DS_DISABLE(i);
+			delay(RETENTION_EXTRA_CYCLES_DELAY);
+			while (!BANK_PWR_STATUS(i))
+				;
+		} else if (!out) {
+			/* enter deep sleep on a bank */
+			BANK_DS_ENABLE(i);
+			while (BANK_PWR_STATUS(i))
 				;
-			__asm__ volatile (
-					"movl $"SLINE(RETENTION_EXIT_CYCLES_DELAY)", %%ecx;"
-					"loop .;\n\t"
-					:
-					:
-					: "ecx"
-					);
 		}
-		mask <<= 1;
-		sum_mask += mask;
 	}
-}
+#else
+	if (out) {
+		/* set main SRAM into normal mode */
+		write32(PMU_LDO_CTRL, PMU_LDO_ENABLE_BIT);
+
+		/*
+		 * poll LDO_READY status to make sure SRAM LDO is on
+		 * (exited retention mode)
+		 */
+		while (!(read32(PMU_LDO_CTRL) & PMU_LDO_READY_BIT))
+			continue;
+	} else {
+		/* set main SRAM into retention mode */
+		write32(PMU_LDO_CTRL, (PMU_LDO_ENABLE_BIT
+					| PMU_LDO_RETENTION_BIT));
+	}
 #endif
+}
 
 static void handle_d0i2(void)
 {
 	pg_exit_save_ctx();
 	aon_share.pg_exit = 0;
 
-#ifdef CONFIG_SOC_INTEL_ISH_5_6_0
-	sram_enter_sleep_mode();
-#else
-	/* set main SRAM into retention mode*/
-	write32(PMU_LDO_CTRL, (PMU_LDO_ENABLE_BIT
-		| PMU_LDO_RETENTION_BIT));
-#endif
+	sram_retention(0);
 	/* delay some cycles before halt */
 	delay(SRAM_RETENTION_CYCLES_DELAY);
 
@@ -646,19 +701,7 @@ static void handle_d0i2(void)
 
 	clear_vnnred_aoncg();
 
-#ifdef CONFIG_SOC_INTEL_ISH_5_6_0
-	sram_exit_sleep_mode();
-#else
-	/* set main SRAM intto normal mode */
-	write32(PMU_LDO_CTRL, PMU_LDO_ENABLE_BIT);
-
-	/**
-	 * poll LDO_READY status to make sure SRAM LDO is on
-	 * (exited retention mode)
-	 */
-	while (!(read32(PMU_LDO_CTRL) & PMU_LDO_READY_BIT))
-		continue;
-#endif
+	sram_retention(1);
 
 	if (read32(PMU_RST_PREP) & PMU_RST_PREP_AVAIL)
 		handle_reset(ISH_PM_STATE_RESET_PREP);

bsp_sedi/soc/intel_ish/pm/ish_dma.c

@@ -1,11 +1,98 @@
 /*
- * Copyright (c) 2023 Intel Corporation
+ * Copyright (c) 2023-2024 Intel Corporation
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "ish_dma.h"
 
+#ifdef CONFIG_SOC_INTEL_ISH_5_8_0
+void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb)
+{
+	/* nothing to do */
+	(void)chan;
+	(void)dst_msb;
+	(void)src_msb;
+}
+
+int ish_dma_copy(uint32_t chan, uint64_t dst, uint64_t src, uint32_t length,
+		enum dma_mode mode)
+{
+	int rc = DMA_RC_OK;
+	uint32_t src_osr_lmt = (mode & SRC_IS_DRAM) ? DMA_OSR_LMT_DRAM : DMA_OSR_LMT_SRAM;
+	uint32_t dst_osr_lmt = (mode & DST_IS_DRAM) ? DMA_OSR_LMT_DRAM : DMA_OSR_LMT_SRAM;
+
+	if (!length) {
+		return DMA_RC_OK;
+	}
+
+	/* Bringup VNN power rail for accessing SoC fabric */
+	write32(PMU_VNN_REQ, (1 << VNN_ID_DMA(chan)));
+	while (!(read32(PMU_VNN_REQ_ACK) & PMU_VNN_REQ_ACK_STATUS))
+		continue;
+
+	write64(DMAC_CFG_REG, DMAC_CFG_EN);
+	mode |= RD_NON_SNOOP | WR_NON_SNOOP;
+	write32(MISC_DMA_CTL_REG(chan), mode);
+	write64(DMA_CH_CTRL_REG(chan), DMA_CH_CTRL_VAL);
+	write64(DMA_CH_CFG2_REG(chan), DMA_CFG_H_VAL(dst_osr_lmt, src_osr_lmt));
+	write64(DMA_CH_LLP_REG(chan), 0x0);
+	write64(DMA_CH_INT_EN_REG(chan), DMA_CH_INT_EN_VAL);
+	write64(DMA_CH_INT_CLR_REG(chan), read64(DMA_CH_INT_STS_REG(chan)));
+
+	while (length) {
+		uint32_t chunk = (length > DMA_MAX_BLOCK_SIZE) ?
+			DMA_MAX_BLOCK_SIZE : length;
+		uint32_t block_ts = chunk >> DMA_SRC_TR_WIDTH;
+
+		if (chunk % block_ts) {
+			block_ts++;
+		}
+		write64(DMA_CH_BLOCK_TS_REG(chan), block_ts - 1);
+
+		write64(DMA_CH_SAR_REG(chan), src);
+		write64(DMA_CH_DAR_REG(chan), dst);
+
+		write64(DMAC_CHEN_REG, DMAC_CHEN_CH_BITS(chan));
+		while (read64(DMAC_CHEN_REG) & DMAC_CHEN_CH_BITS(chan)) {
+			;
+		}
+
+		if (read64(DMA_CH_INT_STS_REG(chan)) != DMA_INT_XFER_DONE) {
+			write64(DMA_CH_INT_CLR_REG(chan), read64(DMA_CH_INT_STS_REG(chan)));
+			rc = DMA_RC_HW;
+			break;
+		}
+		src += chunk;
+		dst += chunk;
+		length -= chunk;
+		write64(DMA_CH_INT_CLR_REG(chan), read64(DMA_CH_INT_STS_REG(chan)));
+	}
+
+	/* Mark the DMA VNN power rail as no longer needed */
+	write32(PMU_VNN_REQ, (1 << VNN_ID_DMA(chan)));
+
+	return rc;
+}
+
+void ish_dma_disable(void)
+{
+	/* Based on [ROM FAS], 2.1.3 "DMA Controller initialization". */
+	uint32_t counter = 0;
+
+	do {
+		++counter;
+	} while ((uint8_t)read64(DMAC_CHEN_REG) && (counter < (UINT32_MAX / 64)));
+
+	if ((uint8_t)read64(DMAC_CHEN_REG))
+		write64(DMAC_RESET_REG, 1);
+
+	write64(DMAC_INTSTS_EN_REG, 0);
+	write64(DMAC_INTSIG_EN_REG, 0);
+	write64(DMAC_INT_CLR_REG, read64(DMAC_INT_STAT_REG));
+	write64(DMAC_CFG_REG, 0);
+}
+#else
 static int dma_init_called; /* If ish_dma_init is called */
 
 static int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask)
@@ -71,7 +158,7 @@ void ish_dma_init(void)
 	dma_init_called = 1;
 }
 
-int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
+int ish_dma_copy(uint32_t chan, uint64_t dst, uint64_t src, uint32_t length,
 		 enum dma_mode mode)
 {
 	uint32_t chan_reg = DMA_REG_BASE + (DMA_CH_REGS_SIZE * chan);
@@ -120,8 +207,8 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
 		eflags = interrupt_lock();
 		write32(MISC_CHID_CFG_REG, chan); /* Set channel to configure */
 		write32(DMA_CTL_HIGH(chan_reg), chunk);	/* Set number of bytes to transfer */
-		write32(DMA_DAR(chan_reg), dst); /* Destination address */
-		write32(DMA_SAR(chan_reg), src); /* Source address */
+		write32(DMA_DAR(chan_reg), (uint32_t)dst); /* Destination address */
+		write32(DMA_SAR(chan_reg), (uint32_t)src); /* Source address */
 		write32(DMA_EN_REG, DMA_CH_EN_BIT(chan) |
 			     DMA_CH_EN_WE_BIT(chan)); /* Enable the channel */
 		interrupt_unlock(eflags);
@@ -178,3 +265,4 @@ void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb)
 	write32(MISC_DST_FILLIN_DMA(chan), dst_msb);
 	interrupt_unlock(eflags);
 }
+#endif