Add Intel FRED and LKGS instructions

icedland · Mar 14, 2021 · 8eb0279 · 8eb0279
1 parent 1450ae2
commit 8eb0279
Show file tree

Hide file tree

Showing 81 changed files with 1,033 additions and 51 deletions.
diff --git a/src/UnitTests/Intel/Decoder/Code.64Only.txt b/src/UnitTests/Intel/Decoder/Code.64Only.txt
@@ -448,3 +448,8 @@ Stui
 Senduipi_r64
 Ccs_hash_64
 Ccs_encrypt_64
+Lkgs_rm16
+Lkgs_r32m16
+Lkgs_r64m16
+Erets
+Eretu
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest64.txt b/src/UnitTests/Intel/Decoder/DecoderTest64.txt
@@ -32527,3 +32527,28 @@ F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64
 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 decopt=Xbts no_opt_disable_test
 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 decopt=Cmpxchg486A no_opt_disable_test
 F3 4F 0FA7 F0, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0
+
+66 F2 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;cx
+F2 66 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;cx enc=66F20F00F1
+66 F2 41 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;r9w
+66 F2 0F00 30, Lkgs_rm16, Lkgs, 1, op0=m;ds;rax;;1;0;0;UInt16
+F2 66 46 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;cx enc=66F20F00F1
+66 F2 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;cx decopt=Jmpe no_opt_disable_test
+
+F2 0F00 F1, Lkgs_r32m16, Lkgs, 1, op0=r;ecx
+F2 41 0F00 F1, Lkgs_r32m16, Lkgs, 1, op0=r;r9d
+F2 0F00 30, Lkgs_r32m16, Lkgs, 1, op0=m;ds;rax;;1;0;0;UInt16
+F2 46 0F00 F1, Lkgs_r32m16, Lkgs, 1, op0=r;ecx enc=F20F00F1
+F2 0F00 F1, Lkgs_r32m16, Lkgs, 1, op0=r;ecx decopt=Jmpe no_opt_disable_test
+
+F2 48 0F00 F1, Lkgs_r64m16, Lkgs, 1, op0=r;rcx
+F2 49 0F00 F1, Lkgs_r64m16, Lkgs, 1, op0=r;r9
+F2 48 0F00 30, Lkgs_r64m16, Lkgs, 1, op0=m;ds;rax;;1;0;0;UInt16
+F2 4E 0F00 F1, Lkgs_r64m16, Lkgs, 1, op0=r;rcx enc=F2480F00F1
+F2 48 0F00 F1, Lkgs_r64m16, Lkgs, 1, op0=r;rcx decopt=Jmpe no_opt_disable_test
+
+F3 0F 01 CA, Eretu, Eretu, 0,
+F3 4F 0F 01 CA, Eretu, Eretu, 0, enc=F30F01CA
+
+F2 0F 01 CA, Erets, Erets, 0,
+F2 4F 0F 01 CA, Erets, Erets, 0, enc=F20F01CA
diff --git a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
@@ -4321,3 +4321,8 @@ Ccs_hash_64, Ccs_hash, Unknown, Unknown, legacy, F3, 0F, A6E8, a64 F3 0F A6 E8,
 Ccs_encrypt_16, Ccs_encrypt, Unknown, Unknown, legacy, F3, 0F, A7F0, a16 F3 0F A7 F0, CCS_ENCRYPT, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
 Ccs_encrypt_32, Ccs_encrypt, Unknown, Unknown, legacy, F3, 0F, A7F0, a32 F3 0F A7 F0, CCS_ENCRYPT, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
 Ccs_encrypt_64, Ccs_encrypt, Unknown, Unknown, legacy, F3, 0F, A7F0, a64 F3 0F A7 F0, CCS_ENCRYPT, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Lkgs_rm16, Lkgs, UInt16, Unknown, legacy, F2, 0F, 00, o16 F2 0F 00 /6, LKGS r/m16, g=6 64 cpl0 o16 op=r16_or_mem intel64 amd64 lm outside-smm in-smm outside-sgx outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam priv
+Lkgs_r32m16, Lkgs, UInt16, Unknown, legacy, F2, 0F, 00, o32 F2 0F 00 /6, LKGS r32/m16, g=6 64 cpl0 o32 op=r32_or_mem intel64 amd64 lm outside-smm in-smm outside-sgx outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam priv
+Lkgs_r64m16, Lkgs, UInt16, Unknown, legacy, F2, 0F, 00, F2 o64 0F 00 /6, LKGS r64/m16, g=6 64 cpl0 o64 op=r64_or_mem intel64 amd64 lm outside-smm in-smm outside-sgx outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam priv
+Erets, Erets, Unknown, Unknown, legacy, F2, 0F, 01CA, F2 0F 01 CA, ERETS, 64 cpl0 stack intel64 amd64 lm outside-smm in-smm outside-sgx outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam priv
+Eretu, Eretu, Unknown, Unknown, legacy, F3, 0F, 01CA, F3 0F 01 CA, ERETU, 64 cpl0 stack intel64 amd64 lm outside-smm in-smm outside-sgx outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam priv
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+lkgs cx
+lkgs [rax]
+lkgs ecx
+lkgs [rax]
+lkgs rcx
+lkgs [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+lkgs cx
+lkgs word ptr ds:[rax]
+lkgs ecx
+lkgs word ptr ds:[rax]
+lkgs rcx
+lkgs word ptr ds:[rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 addr32 rep ccs_hash
 rep ccs_encrypt
 addr32 rep ccs_encrypt
+lkgsw cx
+lkgsw (rax)
+lkgsw cx
+lkgsw (rax)
+lkgsw cx
+lkgsw (rax)
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 addr32 rep ccs_hash
 rep ccs_encrypt
 addr32 rep ccs_encrypt
+lkgs %cx
+lkgs (%rax)
+lkgs %cx
+lkgs (%rax)
+lkgs %cx
+lkgs (%rax)
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt
@@ -8386,3 +8386,11 @@ F3 0FA6 E8, Ccs_hash_64
 67 F3 0FA6 E8, Ccs_hash_32
 F3 0FA7 F0, Ccs_encrypt_64
 67 F3 0FA7 F0, Ccs_encrypt_32
+F2 66 0F00 F1, Lkgs_rm16
+F2 66 0F00 30, Lkgs_rm16
+F2 0F00 F1, Lkgs_r32m16
+F2 0F00 30, Lkgs_r32m16
+F2 48 0F00 F1, Lkgs_r64m16
+F2 48 0F00 30, Lkgs_r64m16
+F3 0F 01 CA, Eretu
+F2 0F 01 CA, Erets
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 addr32 rep ccs_hash
 rep ccs_encrypt
 addr32 rep ccs_encrypt
+lkgs cx
+lkgs word ptr [rax]
+lkgs ecx
+lkgs word ptr [rax]
+lkgs rcx
+lkgs word ptr [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 addr32 rep ccs_hash
 rep ccs_encrypt
 addr32 rep ccs_encrypt
+lkgs cx
+lkgs [rax]
+lkgs ecx
+lkgs [rax]
+lkgs rcx
+lkgs [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 addr32 rep ccs_hash
 rep ccs_encrypt
 addr32 rep ccs_encrypt
+lkgs cx
+lkgs [rax]
+lkgs ecx
+lkgs [rax]
+lkgs rcx
+lkgs [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+lkgs cx
+lkgs word ptr [rax]
+lkgs ecx
+lkgs word ptr [rax]
+lkgs rcx
+lkgs word ptr [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+lkgs cx
+lkgs word ptr [rax]
+lkgs ecx
+lkgs word ptr [rax]
+lkgs rcx
+lkgs word ptr [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+lkgs cx
+lkgs [rax]
+lkgs ecx
+lkgs [rax]
+lkgs rcx
+lkgs [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 a32 rep ccs_hash
 rep ccs_encrypt
 a32 rep ccs_encrypt
+o16 lkgs cx
+o16 lkgs word [rax]
+lkgs cx
+lkgs word [rax]
+o64 lkgs cx
+o64 lkgs word [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 a32 rep ccs_hash
 rep ccs_encrypt
 a32 rep ccs_encrypt
+o16 lkgs cx
+o16 lkgs [rax]
+lkgs cx
+lkgs [rax]
+o64 lkgs cx
+o64 lkgs [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
@@ -8386,3 +8386,11 @@ rep ccs_hash
 a32 rep ccs_hash
 rep ccs_encrypt
 a32 rep ccs_encrypt
+o16 lkgs cx
+o16 lkgs [rax]
+lkgs cx
+lkgs [rax]
+o64 lkgs cx
+o64 lkgs [rax]
+eretu
+erets
diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
@@ -19245,3 +19245,19 @@ F3 0FA6 E8, Ccs_hash_64, Legacy, PADLOCK_GMI, crm=es:rdi;Unknown cwm=es:rdi;Unkn
 67 F3 0FA7 F0, Ccs_encrypt_32, Legacy, PADLOCK_GMI, crm=es:ebx;Unknown crm=es:esi;Unknown cwm=es:edi;Unknown cr=ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx cr=eax
 # rep ccs_encrypt
 F3 0FA7 F0, Ccs_encrypt_64, Legacy, PADLOCK_GMI, crm=es:rbx;Unknown crm=es:rsi;Unknown cwm=es:rdi;Unknown cr=rbx;rsi;rdi cw=rsi;rdi rcw=rcx cr=rax
+# lkgs cx
+F2 66 0F00 F1, Lkgs_rm16, Legacy, LKGS, priv op0=r r=cx w=gs
+# lkgs word ptr [rax]
+F2 66 0F00 30, Lkgs_rm16, Legacy, LKGS, priv op0=r r=rax w=gs rm=ds:rax;UInt16
+# lkgs cx
+F2 0F00 F1, Lkgs_r32m16, Legacy, LKGS, priv op0=r r=cx w=gs
+# lkgs word ptr [rax]
+F2 0F00 30, Lkgs_r32m16, Legacy, LKGS, priv op0=r r=rax w=gs rm=ds:rax;UInt16
+# lkgs cx
+F2 48 0F00 F1, Lkgs_r64m16, Legacy, LKGS, priv op0=r r=cx w=gs
+# lkgs word ptr [rax]
+F2 48 0F00 30, Lkgs_r64m16, Legacy, LKGS, priv op0=r r=rax w=gs rm=ds:rax;UInt16
+# eretu
+F3 0F 01 CA, Eretu, Legacy, FRED, priv flow=Return fw=acopszidA w=cs;ss;rsp rw=xsp rm=ss:xsp;UInt64 rm=ss:xsp+8;UInt64 rm=ss:xsp+0x10;UInt64 rm=ss:xsp+0x18;UInt64 rm=ss:xsp+0x20;UInt64 stack=40
+# erets
+F2 0F 01 CA, Erets, Legacy, FRED, priv flow=Return fw=acopszidA w=rsp rw=xsp rm=ss:xsp;UInt64 rm=ss:xsp+8;UInt64 rm=ss:xsp+0x10;UInt64 rm=ss:xsp+0x18;UInt64 rm=ss:xsp+0x20;UInt64 stack=40
diff --git a/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs b/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs
@@ -880,10 +880,26 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.Ew)], codeEnum[nameof(Code.Verr_rm16)], codeEnum[nameof(Code.Verr_r32m16)], codeEnum[nameof(Code.Verr_r64m16)] },
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.Ew)], codeEnum[nameof(Code.Verw_rm16)], codeEnum[nameof(Code.Verw_r32m16)], codeEnum[nameof(Code.Verw_r64m16)] },
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.Options_DontReadModRM)],
-						invalid,
+						new object[] { legacyEnum[nameof(OpCodeHandlerKind.MandatoryPrefix)],
+							invalid,
+							invalid,
+							invalid,
+							new object[] { legacyEnum[nameof(OpCodeHandlerKind.Bitness_DontReadModRM)],
+								invalid,
+								new object[] { legacyEnum[nameof(OpCodeHandlerKind.Evw)], codeEnum[nameof(Code.Lkgs_rm16)], codeEnum[nameof(Code.Lkgs_r32m16)], codeEnum[nameof(Code.Lkgs_r64m16)] },
+							},
+						},
 						new object[] { legacyEnum[nameof(OpCodeHandlerKind.Bitness_DontReadModRM)],
 							new object[] { legacyEnum[nameof(OpCodeHandlerKind.Ev_3b)], codeEnum[nameof(Code.Jmpe_rm16)], codeEnum[nameof(Code.Jmpe_rm32)] },
-							invalid,
+							new object[] { legacyEnum[nameof(OpCodeHandlerKind.MandatoryPrefix)],
+								invalid,
+								invalid,
+								invalid,
+								new object[] { legacyEnum[nameof(OpCodeHandlerKind.Bitness_DontReadModRM)],
+									invalid,
+									new object[] { legacyEnum[nameof(OpCodeHandlerKind.Evw)], codeEnum[nameof(Code.Lkgs_rm16)], codeEnum[nameof(Code.Lkgs_r32m16)], codeEnum[nameof(Code.Lkgs_r64m16)] },
+								},
+							},
 						}, decoderOptionsEnum[nameof(DecoderOptions.Jmpe)]
 					},
 					invalid,
@@ -976,8 +992,14 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.MandatoryPrefix_NoModRM)],
 						new object[] { legacyEnum[nameof(OpCodeHandlerKind.Simple)], codeEnum[nameof(Code.Clac)] },
 						invalid_NoModRM,
-						invalid_NoModRM,
-						invalid_NoModRM,
+						new object[] { legacyEnum[nameof(OpCodeHandlerKind.Bitness)],
+							invalid_NoModRM,
+							new object[] { legacyEnum[nameof(OpCodeHandlerKind.Simple)], codeEnum[nameof(Code.Eretu)] },
+						},
+						new object[] { legacyEnum[nameof(OpCodeHandlerKind.Bitness)],
+							invalid_NoModRM,
+							new object[] { legacyEnum[nameof(OpCodeHandlerKind.Simple)], codeEnum[nameof(Code.Erets)] },
+						},
 					},
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.MandatoryPrefix_NoModRM)],
 						new object[] { legacyEnum[nameof(OpCodeHandlerKind.Simple)], codeEnum[nameof(Code.Stac)] },

diff --git a/src/csharp/Intel/Generator/Enums/Code.cs b/src/csharp/Intel/Generator/Enums/Code.cs
@@ -4329,6 +4329,11 @@ enum Code {
 		Ccs_encrypt_16,
 		Ccs_encrypt_32,
 		Ccs_encrypt_64,
+		Lkgs_rm16,
+		Lkgs_r32m16,
+		Lkgs_r64m16,
+		Erets,
+		Eretu,
 	}
 
 	[TypeGen(TypeGenOrders.CreatedInstructions)]

diff --git a/src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs b/src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs
@@ -316,5 +316,9 @@ enum CpuidFeature {
 		AVX_VNNI,
 		[Comment("CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.GMI[Bits 5:4] = 11B ([4] = exists, [5] = enabled)")]
 		PADLOCK_GMI,
+		[Comment("CPUID.(EAX=07H, ECX=01H):EAX.FRED[bit 17]")]
+		FRED,
+		[Comment("CPUID.(EAX=07H, ECX=01H):EAX.LKGS[bit 18]")]
+		LKGS,
 	}
 }
diff --git a/src/csharp/Intel/Generator/Enums/Mnemonic.cs b/src/csharp/Intel/Generator/Enums/Mnemonic.cs
@@ -1633,5 +1633,8 @@ enum Mnemonic {
 		Hreset,
 		Ccs_hash,
 		Ccs_encrypt,
+		Lkgs,
+		Erets,
+		Eretu,
 	}
 }