Add RLE encoder #974
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Add RLE encoder #974
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proppy
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Please let me know when you are satisfied with the changes. Then, I will rebase the code to provide a clean git history. |
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I think this is ready to import, most of the changes I requested are purely cosmetic. |
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@proppy can you take a look? Unfortunately I can't mark comments as |
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This is ready to copybara import (remaining comments are mostly cosmetic). |
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I'll change RLEEnc to RunLengthEncoder and squash all commits into single in preparations for merging |
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Currently, only a simple implementation is provided, which has no optimizations related to the RLE algorithm. The provided tests check if: * output of the encoder matches the expected values * sum of received symbols adds up to the amount of sent symbols * received symbols don't repeat unless the RLE counter overflowed or the end of transmission was requested (using `last` flag) Additional bazel rules added in this commit include: * Verilog code generation * IR benchmark generation * Verilog benchmark generation Internal-tag: [#44560] Co-authored-by: Maciej Dudek <mdudek@antmicro.com> Signed-off-by: Robert Winkler <rwinkler@antmicro.com> Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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This PR adds a simple implementation of the RLE Encoder (Run Length Encoding). The introduced changes contain the RLE encoder, tests for the module, rules for Verilog generation, and rules to build IR and Verilog benchmarks.
The changes rely on other features added in separate PRs:
topto the list of valid opt_ir flags #964[DSLX] Add functions that calculate the length of an array to stdlib #973Fixes #994
CC @proppy