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Add tags support for parameters, defines and enum labels
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@gmlarumbe
gmlarumbe committed Oct 7, 2023
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2 changes: 1 addition & 1 deletion test-hdl
Submodule test-hdl updated 98 files
+14 −2 test-hdl-common.el
+4 −4 verilog/files/capf/verilog-ext/ref/tb_program.annotations.el
+3 −3 verilog/files/capf/verilog-ext/ref/ucontroller.annotations.el
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+1,208 −1,138 verilog/files/tags/verilog-ext/ref/axi_demux.refs.el
+233 −115 verilog/files/tags/verilog-ext/ref/axi_demux.ts.defs.el
+1,197 −1,127 verilog/files/tags/verilog-ext/ref/axi_demux.ts.refs.el
+444 −443 verilog/files/tags/verilog-ext/ref/axi_test.defs.el
+4,363 −4,050 verilog/files/tags/verilog-ext/ref/axi_test.refs.el
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+4,336 −4,023 verilog/files/tags/verilog-ext/ref/axi_test.ts.refs.el
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+1 −1 verilog/files/tags/verilog-ext/ref/instances.ts.defs.el
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+19 −19 verilog/files/tags/verilog-ext/ref/tb_program.defs.el
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+128 −126 verilog/files/tags/verilog-ext/ref/tb_program.ts.refs.el
+45 −45 verilog/files/tags/verilog-ext/ref/ucontroller.defs.el
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+51 −45 verilog/files/tags/verilog-ext/ref/ucontroller.ts.defs.el
+186 −184 verilog/files/tags/verilog-ext/ref/ucontroller.ts.refs.el
+127 −127 verilog/files/tags/verilog-ext/ref/uvm_component.defs.el
+2,054 −1,973 verilog/files/tags/verilog-ext/ref/uvm_component.refs.el
+574 −595 verilog/files/tags/verilog-ext/ref/uvm_component.ts.defs.el
+2,054 −1,973 verilog/files/tags/verilog-ext/ref/uvm_component.ts.refs.el
+1 −4 verilog/files/xref/verilog-ext/ref/uvm_component.xref.defs.el
+54 −0 verilog/files/xref/verilog-ext/ref/uvm_component.xref.refs.el
+7 −7 vhdl/files/capf/vhdl-ext/ref/axi_if_converter.annotations.el
+5 −5 vhdl/files/capf/vhdl-ext/ref/axi_if_converter.capf.el
+4 −4 vhdl/files/capf/vhdl-ext/ref/global_sim.annotations.el
+4 −4 vhdl/files/capf/vhdl-ext/ref/global_sim.capf.el
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+1,572 −0 vhdl/files/common/std_logic_1164-body.vhdl
+309 −0 vhdl/files/common/std_logic_1164.vhdl
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+309 −0 vhdl/files/faceup/vhdl-ext/ref/std_logic_1164.faceup
+1 −1 vhdl/files/faceup/vhdl-ts-mode/ref/instances.faceup
+25 −1 vhdl/files/faceup/vhdl-ts-mode/ref/misc.faceup
+3 −3 vhdl/files/faceup/vhdl-ts-mode/ref/sexp.faceup
+1,572 −0 vhdl/files/faceup/vhdl-ts-mode/ref/std_logic_1164-body.faceup
+309 −0 vhdl/files/faceup/vhdl-ts-mode/ref/std_logic_1164.faceup
+1 −1 vhdl/files/faceup/vhdl-ts-mode/ref/tb_axi_if_converter.faceup
+5 −2 vhdl/files/imenu/vhdl-ext/ref/misc.el
+85 −0 vhdl/files/imenu/vhdl-ext/ref/std_logic_1164-body.el
+82 −0 vhdl/files/imenu/vhdl-ext/ref/std_logic_1164.el
+5 −1 vhdl/files/imenu/vhdl-ts-mode/ref/misc.el
+82 −0 vhdl/files/imenu/vhdl-ts-mode/ref/std_logic_1164-body.el
+1 −0 vhdl/files/imenu/vhdl-ts-mode/ref/std_logic_1164.el
+25 −1 vhdl/files/indent/vhdl-ts-mode/ref/misc.no_deindent.vhd
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+1,572 −0 vhdl/files/indent/vhdl-ts-mode/ref/std_logic_1164-body.no_deindent.vhd
+1,572 −0 vhdl/files/indent/vhdl-ts-mode/ref/std_logic_1164-body.vhdl
+309 −0 vhdl/files/indent/vhdl-ts-mode/ref/std_logic_1164.no_deindent.vhd
+309 −0 vhdl/files/indent/vhdl-ts-mode/ref/std_logic_1164.vhdl
+1 −1 vhdl/files/navigation/vhdl-ext/ref/block0.rg
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+1 −1 vhdl/files/navigation/vhdl-ts-mode/ref/misc.block.bwd.el
+1 −1 vhdl/files/navigation/vhdl-ts-mode/ref/misc.block.fwd.el
+1 −0 vhdl/files/navigation/vhdl-ts-mode/ref/std_logic_1164-body.block.bwd.el
+1 −0 vhdl/files/navigation/vhdl-ts-mode/ref/std_logic_1164-body.block.fwd.el
+1 −0 vhdl/files/navigation/vhdl-ts-mode/ref/std_logic_1164.block.bwd.el
+1 −0 vhdl/files/navigation/vhdl-ts-mode/ref/std_logic_1164.block.fwd.el
+480 −724 vhdl/files/tags/vhdl-ext/ref/axi_if_converter.ts.defs.el
+2,375 −1,968 vhdl/files/tags/vhdl-ext/ref/axi_if_converter.ts.refs.el
+58 −93 vhdl/files/tags/vhdl-ext/ref/global_pkg.ts.defs.el
+130 −141 vhdl/files/tags/vhdl-ext/ref/global_pkg.ts.refs.el
+307 −282 vhdl/files/tags/vhdl-ext/ref/global_sim.ts.defs.el
+841 −547 vhdl/files/tags/vhdl-ext/ref/global_sim.ts.refs.el
+1,448 −1,805 vhdl/files/tags/vhdl-ext/ref/hierarchy.ts.defs.el
+8,357 −5,535 vhdl/files/tags/vhdl-ext/ref/hierarchy.ts.refs.el
+12 −16 vhdl/files/tags/vhdl-ext/ref/indent_misc.ts.defs.el
+78 −89 vhdl/files/tags/vhdl-ext/ref/indent_misc.ts.refs.el
+24 −34 vhdl/files/tags/vhdl-ext/ref/instances.ts.defs.el
+157 −129 vhdl/files/tags/vhdl-ext/ref/instances.ts.refs.el
+6 −6 vhdl/files/tags/vhdl-ext/ref/misc.ts.defs.el
+48 −24 vhdl/files/tags/vhdl-ext/ref/misc.ts.refs.el
+78 −79 vhdl/files/tags/vhdl-ext/ref/sexp.ts.defs.el
+235 −174 vhdl/files/tags/vhdl-ext/ref/sexp.ts.refs.el
+645 −0 vhdl/files/tags/vhdl-ext/ref/std_logic_1164-body.ts.defs.el
+3,733 −0 vhdl/files/tags/vhdl-ext/ref/std_logic_1164-body.ts.refs.el
+369 −0 vhdl/files/tags/vhdl-ext/ref/std_logic_1164.ts.defs.el
+971 −0 vhdl/files/tags/vhdl-ext/ref/std_logic_1164.ts.refs.el
+362 −547 vhdl/files/tags/vhdl-ext/ref/tb_axi_if_converter.ts.defs.el
+1,841 −1,445 vhdl/files/tags/vhdl-ext/ref/tb_axi_if_converter.ts.refs.el
+1 −0 vhdl/files/utils/vhdl-ext/ref/std_logic_1164-body.scan.entities.el
+1 −0 vhdl/files/utils/vhdl-ext/ref/std_logic_1164.scan.entities.el
+843 −111 vhdl/files/xref/vhdl-ext/ref/axi_if_converter.xref.defs.el
+3,768 −804 vhdl/files/xref/vhdl-ext/ref/axi_if_converter.xref.refs.el
+151 −15 vhdl/files/xref/vhdl-ext/ref/global_sim.xref.defs.el
+712 −68 vhdl/files/xref/vhdl-ext/ref/global_sim.xref.refs.el
+53 −62 vhdl/vhdl-ext/test-hdl-vhdl-ext-capf.el
+116 −129 vhdl/vhdl-ext/test-hdl-vhdl-ext-hierarchy.el
+2 −2 vhdl/vhdl-ext/test-hdl-vhdl-ext-navigation.el
+53 −75 vhdl/vhdl-ext/test-hdl-vhdl-ext-tags.el
+8 −8 vhdl/vhdl-ext/test-hdl-vhdl-ext-xref.el
27 changes: 18 additions & 9 deletions verilog-ext-tags.el
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@


;;;; Common
(cl-defun verilog-ext-tags-table-push (&key table tag type desc file parent)
(cl-defun verilog-ext-tags-table-push (&key table tag type desc file line col parent)
"Add entry for TAG in hash-table TABLE.
It is needed to provide TYPE, description DESC and FILE properties to add the
Expand All @@ -63,22 +63,23 @@ existing one with current location properties."
(puthash parent parent-value table)))
;; Next add the tag if it was not present in the table or update existing tag properties if it was present.
(if (not tag-value)
(puthash tag `(:items nil :locs (,(verilog-ext-tags-locs-props type desc file))) table)
(puthash tag `(:items nil :locs (,(verilog-ext-tags-locs-props type desc file (line-number-at-pos) (current-column)))) table)
(setq locs-plist (plist-get tag-value :locs))
(setq loc-new (verilog-ext-tags-locs-props type desc file))
(setq loc-new (verilog-ext-tags-locs-props type desc file (line-number-at-pos) (current-column)))
(unless (member loc-new locs-plist)
(push loc-new locs-plist)
(plist-put tag-value :locs locs-plist)
(puthash tag `(:items ,(plist-get tag-value :items) :locs ,locs-plist) table)))))

(defun verilog-ext-tags-locs-props (type desc &optional file)
(defun verilog-ext-tags-locs-props (type desc file line col)
"Return :locs properties for current tag.
These include tag TYPE, description DESC, the FILE and current line."
These include tag TYPE, description DESC, the FILE, current LINE and COL."
`(:type ,type
:desc ,desc
:file ,(or file buffer-file-name)
:line ,(line-number-at-pos)))
:file ,file
:line ,line
:col ,col))

(defun verilog-ext-tags-desc ()
"Return string description for tag at point.
Expand Down Expand Up @@ -293,7 +294,12 @@ buffer."
"variable_decl_assignment"
"net_decl_assignment"
"local_parameter_declaration"
"parameter_declaration"
"type_declaration"
;; Defines
"text_macro_definition"
;; Enum labels
"enum_name_declaration"
;; Instances
"module_instantiation"
"interface_instantiation")
Expand Down Expand Up @@ -367,7 +373,10 @@ completion and navigation."
(let* ((ts-node (car node))
(children (cdr node))
(ts-type (treesit-node-type ts-node))
(is-instance (and ts-type (string-match "\\(module\\|interface\\)_instantiation" ts-type))))
(is-instance (and ts-type (string-match "\\(module\\|interface\\)_instantiation" ts-type)))
(is-typedef-class (and ts-type
(string-match "\\<type_declaration\\>" ts-type)
(string-match (concat "typedef\\s-+class\\s-+" verilog-identifier-re "\\s-*;") (treesit-node-text ts-node :no-prop)))))
;; Iterate over all the nodes of the tree
(mapc (lambda (child-node)
(verilog-ext-tags-table-push-defs-ts--recurse :table table
Expand All @@ -377,7 +386,7 @@ completion and navigation."
:file file))
children)
;; Push definitions of current node
(when ts-node ; root ts-node will be nil
(when (and ts-node (not is-typedef-class)) ; root ts-node will be nil
(goto-char (treesit-node-start ts-node))
(if is-instance
(verilog-ext-tags-table-push :table inst-table
Expand Down

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