Add TL-Verilog

[adamint]

This PR is to add TL-Verilog, an EDA language that transpiles to SystemVerilog and Verilog.

A little about TLV
TL-Verilog is rapidly gaining popularity for digital logic design, as an extension to Verilog (the predominant logic design language). TL-Verilog is utilized within the makerchip.com and edaplayground.com platforms and is supported by tl-x.org. GitHub integration for Makerchip is in the works.

The most popular TL-Verilog projects are:

• https://github.com/stevehoover/warp-v
• https://github.com/stevehoover/1st-CLaaS
  These have numerous forks, stars, and external contributions.

RISC-V International lists popular RISC-V CPU core implementations, including two in TL-Verilog: https://riscv.org/exchange/cores-socs/, one from above, and one from training classes.

Thousands of students have developed using TL-Verilog in online courses:

• Linux Foundation: https://www.edx.org/course/building-a-risc-v-cpu-core
• https://www.vlsisystemdesign.com/riscv-based-myth/,
• https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-verilog/.
  and more are on the way from IEEE (https://events.vtools.ieee.org/m/248362) and Open-Source FPGA Foundation (https://osfpga.org/).

Checklist:

• I am adding a new language.
  • The extension of the new language is used in hundreds of repositories on GitHub.com.
    • Search results for each extension:
      • https://github.com/search?utf8=%E2%9C%93&type=Code&ref=searchresults&q=extension%3Atlv+NOT+nothack
  • I have included a real-world usage sample for all extensions added in this PR:
    • Sample source(s):
      • [URL to each sample source, if applicable]
    • Sample license(s):
  • I have included a syntax highlighting grammar: https://github-lightshow.herokuapp.com/?utf8=%E2%9C%93&scope=from-url&grammar_format=auto&grammar_url=https%3A%2F%2Fraw.githubusercontent.com%2Fadamint%2Ftlv-vscode%2Fmain%2Fsyntaxes%2Ftlverilog.tmLanguage&grammar_text=&code_source=from-url&code_url=https%3A%2F%2Fgithub.com%2Fstevehoover%2Fwarp-v%2Fblob%2Fmaster%2Fwarp-v_config.tlv&code=
  • I have updated the heuristics to distinguish my language from others using the same extension.

[lildude]

Thanks for the PR. If we use your heuristic to filter the search results - like this - we get only 32 files on the whole of GitHub. This is a long way from our minimum requirement of 200 unique :user/:repo repositories so we can't accept this PR right now. Given the very low numbers it's probably best to close this PR and open a new one once usage meets our requirements.

[adamint]

@lildude I'm not sure you put in the right search 😄 \TLV_version and \m4_TLV_version are both supported (and anything actually before TLV)

[lildude]

🤦 I missed that the search has changed and isn't matching the TLV_version part of m4_TLV_version. That said, adjusting the search to take this into account extension:tlv TLV version and pull in even more results which may not all be TL-Verilog files stills comes up considerably short:

Total files found: 457
Unique public user/repos: 81
Unique owners: 47

Even adding together the two individual specific searches doesn't meet the threshold yet:

• extension:tlv TLV_version:

Total files found: 32
Unique public user/repos: 3
Unique owners: 3

• extension:tlv m4_TLV_version:

Total files found: 405
Unique public user/repos: 77
Unique owners: 41

[lildude]

Looks like things are popular enough to merge this PR. Please merge in master and address the conflicts.

[lildude]

Looks like things are popular enough to merge this PR. Please merge in master and address the conflicts.

Or you can grant me write access and I'll do it.

[lildude]

Please resolve the merge conflicts or grant me write access so we can merge this PR.

[lildude]

LGTM. Thanks.

Note: this PR will not be merged until close to when the next release is made. See here for more details.