Xtensa patches (18.x) (Do not merge, PR created for easier review only) #94
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Also lower SHL, SRA, SRL with register operands.
patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.
Add support for llvm.{frameaddress,returnaddress} intrinsics.
Implement volatile load/store from/to volatile memory location.
scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used.
Also implement User Registers class.
Implement DAG Combine for BRCOND operation with f32 operands.
Implement Debug, DFPAccel, S32C1I, THREADPTR, Extended L32R, ATOMCTL, MEMCTL features.
Implement Exception, HighPriInterrupts, Coprocessor, Interrupt, RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR features. Implement instructions for Exception, Interrupt and RegionProtection features with tests.
Make ESP32 default subtarget.
Implement subtarget dependent SR and UR register parsing and disassembling, add tests. Implement User Registers read/write instructions and add tests.
Implement Xtensa specific streamer to support emit literals.
Implement special processing of MOVI and L32R instructions in assembler parser. The MOVI assembler expression now can have 32-bit immediate values, so also correct xtensa-invalid.s test. Also implement computation of CFA during XtensaMCAsmInfo creation.
Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands.
It was changed in LLVM 18
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