Merge branch 'refactor/riscv_interrupt' into 'master'

refactor(riscv): Refactor crosscore interrupts and core interrupt code

Closes IDF-5720, DOC-5177, and IDF-7899

See merge request espressif/esp-idf!27845

components/bt/controller/esp32c3/bt.c

@@ -463,9 +463,8 @@ static void interrupt_set_wrapper(int cpu_no, int intr_source, int intr_num, int
 {
     esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
 #if __riscv
-    esprv_intc_int_set_priority(intr_num, intr_prio);
-    //esprv_intc_int_enable_level(1 << intr_num);
-    esprv_intc_int_set_type(intr_num, 0);
+    esprv_int_set_priority(intr_num, intr_prio);
+    esprv_int_set_type(intr_num, 0);
 #endif
 }
 

components/esp_hw_support/include/esp_cpu.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -261,7 +261,7 @@ FORCE_INLINE_ATTR void esp_cpu_intr_set_type(int intr_num, esp_cpu_intr_type_t i
 {
     assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
     enum intr_type type = (intr_type == ESP_CPU_INTR_TYPE_LEVEL) ? INTR_TYPE_LEVEL : INTR_TYPE_EDGE;
-    esprv_intc_int_set_type(intr_num, type);
+    esprv_int_set_type(intr_num, type);
 }
 
 /**
@@ -276,7 +276,7 @@ FORCE_INLINE_ATTR void esp_cpu_intr_set_type(int intr_num, esp_cpu_intr_type_t i
 FORCE_INLINE_ATTR esp_cpu_intr_type_t esp_cpu_intr_get_type(int intr_num)
 {
     assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
-    enum intr_type type = esprv_intc_int_get_type(intr_num);
+    enum intr_type type = esprv_int_get_type(intr_num);
     return (type == INTR_TYPE_LEVEL) ? ESP_CPU_INTR_TYPE_LEVEL : ESP_CPU_INTR_TYPE_EDGE;
 }
 
@@ -291,7 +291,7 @@ FORCE_INLINE_ATTR esp_cpu_intr_type_t esp_cpu_intr_get_type(int intr_num)
 FORCE_INLINE_ATTR void esp_cpu_intr_set_priority(int intr_num, int intr_priority)
 {
     assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
-    esprv_intc_int_set_priority(intr_num, intr_priority);
+    esprv_int_set_priority(intr_num, intr_priority);
 }
 
 /**
@@ -306,7 +306,7 @@ FORCE_INLINE_ATTR void esp_cpu_intr_set_priority(int intr_num, int intr_priority
 FORCE_INLINE_ATTR int esp_cpu_intr_get_priority(int intr_num)
 {
     assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
-    return esprv_intc_int_get_priority(intr_num);
+    return esprv_int_get_priority(intr_num);
 }
 #endif // SOC_CPU_HAS_FLEXIBLE_INTC
 

components/esp_hw_support/port/esp32c3/esp_memprot.c

@@ -630,8 +630,8 @@ static esp_err_t esp_mprot_set_intr_matrix(const esp_mprot_mem_t mem_type)
     }
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_MEMPROT_ERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_MEMPROT_ERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_INTR_ENABLE(ETS_MEMPROT_ERR_INUM);
 

components/esp_system/crosscore_int.c

@@ -10,7 +10,7 @@
 #include "esp_intr_alloc.h"
 #include "esp_debug_helpers.h"
 #include "soc/periph_defs.h"
-
+#include "hal/crosscore_int_ll.h"
 
 #include "freertos/FreeRTOS.h"
 #include "freertos/portmacro.h"
@@ -19,15 +19,6 @@
 #include "esp_gdbstub.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
-#include "soc/dport_reg.h"
-#else
-#include "soc/system_reg.h"
-#endif
-#if CONFIG_IDF_TARGET_ESP32P4
-#include "soc/hp_system_reg.h"
-#endif
-
 #define REASON_YIELD            BIT(0)
 #define REASON_FREQ_SWITCH      BIT(1)
 #define REASON_PRINT_BACKTRACE  BIT(2)
@@ -53,29 +44,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
     volatile uint32_t *my_reason=arg;
 
     //Clear the interrupt first.
-#if CONFIG_IDF_TARGET_ESP32
-    if (esp_cpu_get_core_id()==0) {
-        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
-    } else {
-        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
-    }
-#elif CONFIG_IDF_TARGET_ESP32S2
-    DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
-#elif CONFIG_IDF_TARGET_ESP32S3
-    if (esp_cpu_get_core_id()==0) {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
-    } else {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
-    }
-#elif CONFIG_IDF_TARGET_ESP32P4
-    if (esp_cpu_get_core_id() == 0) {
-        WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, 0);
-    } else {
-        WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, 0);
-    }
-#elif CONFIG_IDF_TARGET_ARCH_RISCV
-    WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
-#endif
+    crosscore_int_ll_clear_interrupt(esp_cpu_get_core_id());
 
     //Grab the reason and clear it.
     portENTER_CRITICAL_ISR(&reason_spinlock);
@@ -142,29 +111,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
     reason[core_id] |= reason_mask;
     portEXIT_CRITICAL_ISR(&reason_spinlock);
     //Poke the other CPU.
-#if CONFIG_IDF_TARGET_ESP32
-    if (core_id==0) {
-        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
-    } else {
-        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
-    }
-#elif CONFIG_IDF_TARGET_ESP32S2
-    DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
-#elif CONFIG_IDF_TARGET_ESP32S3
-    if (core_id==0) {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
-    } else {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
-    }
-#elif CONFIG_IDF_TARGET_ESP32P4
-    if (core_id==0) {
-        WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, HP_SYSTEM_CPU_INT_FROM_CPU_0);
-    } else {
-        WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, HP_SYSTEM_CPU_INT_FROM_CPU_1);
-    }
-#elif CONFIG_IDF_TARGET_ARCH_RISCV
-    WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
-#endif
+    crosscore_int_ll_trigger_interrupt(core_id);
 }
 
 void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)

components/esp_system/hw_stack_guard.c

@@ -40,8 +40,8 @@ ESP_SYSTEM_INIT_FN(esp_hw_stack_guard_init, SECONDARY, ESP_SYSTEM_INIT_ALL_CORES
     /* enable interrup routine  */
     esp_rom_route_intr_matrix(core_id, ETS_ASSIST_DEBUG_INTR_SOURCE, ETS_ASSIST_DEBUG_INUM);
 
-    esprv_intc_int_set_type(ETS_ASSIST_DEBUG_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_ASSIST_DEBUG_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_ASSIST_DEBUG_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_ASSIST_DEBUG_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_INTR_ENABLE(ETS_ASSIST_DEBUG_INUM);
     return ESP_OK;

components/esp_system/include/esp_private/crosscore_int.h

@@ -50,7 +50,7 @@ void esp_crosscore_int_send_freq_switch(int core_id);
 
 void esp_crosscore_int_send_gdb_call(int core_id);
 
-#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 /**
  * Send an interrupt to a CPU indicating it should print its current backtrace
  *
@@ -75,7 +75,7 @@ void esp_crosscore_int_send_print_backtrace(int core_id);
 void esp_crosscore_int_send_twdt_abort(int core_id);
 
 #endif // CONFIG_ESP_TASK_WDT_EN
-#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6
+#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 
 #ifdef __cplusplus
 }

components/esp_system/port/cpu_start.c

@@ -68,13 +68,16 @@
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rtc.h"
 #include "soc/hp_sys_clkrst_reg.h"
-#include "soc/interrupt_core0_reg.h"
-#include "soc/interrupt_core1_reg.h"
 #include "soc/keymng_reg.h"
 #endif
 
 #include "esp_private/rtc_clk.h"
 #include "esp_private/esp_ldo_psram.h"
+
+#if SOC_INT_CLIC_SUPPORTED
+#include "hal/interrupt_clic_ll.h"
+#endif // SOC_INT_CLIC_SUPPORTED
+
 #include "esp_private/esp_mmu_map_private.h"
 #if CONFIG_SPIRAM
 #include "esp_psram.h"
@@ -159,21 +162,17 @@ static void core_intr_matrix_clear(void)
     uint32_t core_id = esp_cpu_get_core_id();
 
     for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
-#if CONFIG_IDF_TARGET_ESP32P4
-        if (core_id == 0) {
-            REG_WRITE(INTERRUPT_CORE0_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
-        } else {
-            REG_WRITE(INTERRUPT_CORE1_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
-        }
+#if SOC_INT_CLIC_SUPPORTED
+        interrupt_clic_ll_route(core_id, i, ETS_INVALID_INUM);
 #else
         esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
-#endif  // CONFIG_IDF_TARGET_ESP32P4
+#endif  // SOC_INT_CLIC_SUPPORTED
     }
 
 #if SOC_INT_CLIC_SUPPORTED
     for (int i = 0; i < 32; i++) {
         /* Set all the CPU interrupt lines to vectored by default, as it is on other RISC-V targets */
-        esprv_intc_int_set_vectored(i, true);
+        esprv_int_set_vectored(i, true);
     }
 #endif // SOC_INT_CLIC_SUPPORTED
 

components/esp_system/port/soc/esp32c2/cache_err_int.c

@@ -166,8 +166,8 @@ void esp_cache_err_int_init(void)
     esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* On the hardware side, start by clearing all the bits reponsible for cache access error */

components/esp_system/port/soc/esp32c3/cache_err_int.c

@@ -165,8 +165,8 @@ void esp_cache_err_int_init(void)
     esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* On the hardware side, start by clearing all the bits reponsible for cache access error */

components/esp_system/port/soc/esp32c6/cache_err_int.c

@@ -57,8 +57,8 @@ void esp_cache_err_int_init(void)
     esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* On the hardware side, start by clearing all the bits reponsible for cache access error */

components/esp_system/port/soc/esp32h2/cache_err_int.c

@@ -56,8 +56,8 @@ void esp_cache_err_int_init(void)
     esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* On the hardware side, start by clearing all the bits reponsible for cache access error */

components/esp_system/port/soc/esp32p4/cache_err_int.c

@@ -52,8 +52,8 @@ void esp_cache_err_int_init(void)
     esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
 
     /* Set the type and priority to cache error interrupts. */
-    esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
-    esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
+    esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* On the hardware side, start by clearing all the bits reponsible for cache access error */

components/esp_wifi/esp32c2/esp_adapter.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -105,9 +105,9 @@ static void wifi_delete_queue_wrapper(void *queue)
 
 static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
 {
-    intr_matrix_route(intr_source, intr_num);
-    esprv_intc_int_set_priority(intr_num, intr_prio);
-    esprv_intc_int_set_type(intr_num, INTR_TYPE_LEVEL);
+    esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
+    esprv_int_set_priority(intr_num, intr_prio);
+    esprv_int_set_type(intr_num, INTR_TYPE_LEVEL);
 }
 
 static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)
@@ -122,12 +122,12 @@ static void set_isr_wrapper(int32_t n, void *f, void *arg)
 
 static void enable_intr_wrapper(uint32_t intr_mask)
 {
-    esprv_intc_int_enable(intr_mask);
+    esprv_int_enable(intr_mask);
 }
 
 static void disable_intr_wrapper(uint32_t intr_mask)
 {
-    esprv_intc_int_disable(intr_mask);
+    esprv_int_disable(intr_mask);
 }
 
 static bool IRAM_ATTR is_from_isr_wrapper(void)

components/esp_wifi/esp32c3/esp_adapter.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -108,9 +108,9 @@ static void wifi_delete_queue_wrapper(void *queue)
 
 static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
 {
-    intr_matrix_route(intr_source, intr_num);
-    esprv_intc_int_set_priority(intr_num, intr_prio);
-    esprv_intc_int_set_type(intr_num, INTR_TYPE_LEVEL);
+    esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
+    esprv_int_set_priority(intr_num, intr_prio);
+    esprv_int_set_type(intr_num, INTR_TYPE_LEVEL);
 }
 
 static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)
@@ -125,12 +125,12 @@ static void set_isr_wrapper(int32_t n, void *f, void *arg)
 
 static void enable_intr_wrapper(uint32_t intr_mask)
 {
-    esprv_intc_int_enable(intr_mask);
+    esprv_int_enable(intr_mask);
 }
 
 static void disable_intr_wrapper(uint32_t intr_mask)
 {
-    esprv_intc_int_disable(intr_mask);
+    esprv_int_disable(intr_mask);
 }
 
 static bool IRAM_ATTR is_from_isr_wrapper(void)

components/esp_wifi/esp32c6/esp_adapter.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -111,9 +111,9 @@ static void wifi_delete_queue_wrapper(void *queue)
 
 static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
 {
-    intr_matrix_route(intr_source, intr_num);
-    esprv_intc_int_set_priority(intr_num, intr_prio);
-    esprv_intc_int_set_type(intr_num, INTR_TYPE_LEVEL);
+    esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
+    esprv_int_set_priority(intr_num, intr_prio);
+    esprv_int_set_type(intr_num, INTR_TYPE_LEVEL);
 }
 
 static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)
@@ -128,12 +128,12 @@ static void set_isr_wrapper(int32_t n, void *f, void *arg)
 
 static void enable_intr_wrapper(uint32_t intr_mask)
 {
-    esprv_intc_int_enable(intr_mask);
+    esprv_int_enable(intr_mask);
 }
 
 static void disable_intr_wrapper(uint32_t intr_mask)
 {
-    esprv_intc_int_disable(intr_mask);
+    esprv_int_disable(intr_mask);
 }
 
 static bool IRAM_ATTR is_from_isr_wrapper(void)