Merge branch 'bugfix/ulp_riscv_i2c_example_crashes_on_s2_v4.4' into '…

…release/v4.4' ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 (v4.4) See merge request espressif/esp-idf!21861
espressif · Feb 7, 2023 · 80d81c6 · 80d81c6
2 parents 3cf24d8 + 96b152a
commit 80d81c6
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Showing 2 changed files with 2 additions and 9 deletions.
diff --git a/components/ulp/ulp_riscv.c b/components/ulp/ulp_riscv.c
@@ -32,8 +32,6 @@ esp_err_t ulp_riscv_run(void)
 #if CONFIG_IDF_TARGET_ESP32S2
     /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
-    esp_rom_delay_us(20);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
      /* The coprocessor cpu trap signal doesnt have a stable reset value,
        force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
@@ -57,8 +55,6 @@ esp_err_t ulp_riscv_run(void)
 #elif CONFIG_IDF_TARGET_ESP32S3
     /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
-    esp_rom_delay_us(20);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
      /* The coprocessor cpu trap signal doesnt have a stable reset value,
        force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/

diff --git a/components/ulp/ulp_riscv/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_riscv_utils.c
@@ -31,11 +31,8 @@ void ulp_riscv_shutdown(void)
     /* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */
     REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F);
 
-    /* suspends the ulp operation*/
-    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
-
-    /* Resets the processor */
-    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
+    /* Suspends the ulp operation and reset the ULP core. Must be the final operation before going to halt. */
+    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
 
     while(1);
 }